Delta-sigma modulation

Résumé

Delta-sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is an oversampling method for encoding signals into low bit depth digital signals at a very high sample-frequency as part of the process of delta-sigma analog-to-digital converter (ADCs) and digital-to-analog converters (DACs). Delta-sigma modulation achieves high quality by utilizing a negative feedback loop during quantization to the lower bit depth that continuously corrects quantization errors and moves quantization noise to higher frequencies well above the original signal's bandwidth. Subsequent low-pass filtering for demodulation easily removes this high frequency noise and time averages to achieve high accuracy in amplitude. Both ADCs and DACs can employ delta-sigma modulation. A delta-sigma ADC (e.g. Figure 1 top) encodes an analog signal using high-frequency delta-sigma modulation and then applies a digital filter to demodulate it to a high-bit digital output at a lower sampling-frequency. A delta-sigma DAC (e.g. Figur

Source officielle

https://en.wikipedia.org/wiki/Delta-sigma_modulation

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This lecture provides insights in the design and technologies of Internet-of-Things sensor nodes, with focus on low power technologies. The lectures alternate every two weeks between sensing technologies of various kinds (prof. Ionescu) and their integrated circuit readouts (prof. Enz).

This course is aimed at providing engineers with up-to-date information on important current issues of design in analog and mixed-mode integrated circuits. In general, the content of the lectures covers introduction, state-of-the-art in the specific field and practical case studies.

The course is covering following aspects: MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design, Noise Performance of Elementary Transistor Stages, Stability of Operational Amplifiers, Important Opamp Configurations and Distortion in Elementary Transistor Circuits.

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This paper describes an all-digital backscatter modulation approach leveraging delta-sigma modulation (DSM) to improve the in-channel spectral characteristics of orthogonal frequency division multiplexed (OFDM) backscatter communication. We demonstrate through numerical simulations and experimental validation that DSM can improve the spurious-free dynamic range (SFDR) of OFDM subcarriers generated by a low-resolution impedance digital-to-analog converter (DAC), such as an RF switch having two or four different impedance states. We present the design and validation of a prototype OFDM backscatter uplink with DSM implemented with all-digital logic in an FPGA. A single-pole-four-throw CMOS RF switch (i.e. 2-bits of impedance DAC resolution) serves as the backscatter modulator. We experimentally validated the DSM approach with a 2.4 GHz, five-subcarrier OFDM backscatter uplink and a four-times oversampling DSM at up to 1.25 Mbps. In this scenario, the DSM improved the SFDR by 43 dB within the subcarrier band while reducing the overall noise floor in the same band by 11.3 dB. These results confirm that a DSM approach can be used to control quantization noise and improve the spectral characteristics of low-resolution digital impedance modulators for backscatter communication in scenarios where in-channel SFDR is more important than wideband noise performance.

IEEE2022

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Low power frequency synthesizer for mobile communications systems

Imre Kovacs

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).

EPFL2009

Chargement

Silicon on Insulator (SOI) is an interesting alternative to bulk silicon for the fabrication of integrated circuits due to its advantages with respect to the junction leakage, low switching noise coupling, high temperature immunity, low voltage and low power applications. Recently, SOI transistors have also been used in high speed CPU's due to their high switching performances and their reduced power consumption. Another application where high performances and even higher densities are needed are dynamic memories (DRAM) where floating body SOI MOSFETS were used as an 1T memory node. Using the floating body as a charge storage reduces the unit cell size and drastically increases the bit density and the storage capacity. However, despite technical advances in SOI technology, it has rarely been exploited in optical sensing and imagery. The main reasons are the expected low optical conversion efficiency due to the relatively thin silicon film thicknesses, well below 1 µm and the slow time constants due to slow recombinations at the junctions. In addition, the slim active region reduces the optical bandwidth of such sensors as longer wavelengths are absorbed deeper (and in the case of SOI probably in the buried oxide layer). Despite these major handicaps, it was shown recently that an SOI MOSFET based phototransistor could detect light intensities as low as 5 mW/m2. However, previous work addressed only low light intensities neglecting the slow transients drawbacks. Moreover, as for most fully and partially depleted SOI MOSFET's based photodetectors, it is the drain current variation due to light absorption that was used as a measure of photon densities (for instance the 5 mW/m2 generates 50 fA of photocurrent). Such variations are hard to measure with the needed resolution as such currents are close to the noise levels of any amplifier. This research project proposes a new measurement technique that does not rely on direct quantification of the photocurrent and hence overcomes the problems inherent to noise and low current variations. In addition to that, this novel technique solves the problem of slow drain current recovery time inherent to the slow recombinations at the junctions. This technique relies on the transient charge pumping used to remove continuously photogenerated charges from the electrically insulated body of the MOSFET. Then, since the transistor is always maintained in equilibrium conditions, this approach will get rid of any transient effect occurring in the partially depleted SOI MOSFET. Also presented in this work is an extension of this technique to any floating body MOSFET. We presented also measurement of bulk P-MOSFET whose n-well was left floating and showed that the behaviour was similar to that of a floating body SOI MOSFET. Still using the transient charge pumping to remove extra charge from the floating n-well. Finally, An SOI circuit implementation of this technique was presented. This circuit takes advantage of some of the properties of the floating body SOI MOSFET to implement a first order delta sigma modulator at the pixel level without substantially reducing the fill factor. The first order delta sigma modulator in each pixel, can improve the resolution and offer a direct digital output without the need of an ADC.

EPFL2009

Chargement

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

EPFL2009