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Concept
Current-mode logic
Résumé
Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signaling of digital data.
The basic principle of CML is that current from a constant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented. Typically, the generator is connected to the two sources of a pair of differential FETs, with the two paths being their two drains. Bipolar equivalents operate similarly, with the output being taken from the collectors of the BJT transistors.
As a differential PCB-level interconnect, it is intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s across standard printed circuit boards.
The transmission is point-to-point, unidirectional, and is usually terminated at the destination with 50 Ω resistors to Vcc on both differential lines. CML is frequently used in interfaces to fiber optic components. The principle difference between CML and ECL as a link technology is the output impedance of the driver stage: the emitter follower of ECL has a low resistance of around 5 Ω whereas CML connects to the drains of the driving transistors, that have a high impedance, and so the impedance of the pull up/down network (typically 50 Ω resistive) is the effective output impedance. Matching this drive impedance close to the driven transmission line's characteristic impedance greatly reduces undesirable ringing.
CML signals have also been found useful for connections between modules. CML is the physical layer used in DVI, HDMI and FPD-Link III video links, the interfaces between a display controller and a monitor.
In addition, CML has been widely used in high-speed integrated systems, such as for serial data transceivers and frequency synthesizers in telecommunication systems.
The fast operation of CML circuits is mainly due to their lower output voltage swing compared to the static CMOS circuits, as well as the very fast current switching taking place at the input differential pair transistors.
Source officielle
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