Publications associées à Semiconductor intellectual property core

Rachid Guerraoui, Maysam Yabandeh, Tudor Alexandru David

Scaling to a large number of cores with non-uniform communication latency and unpredictable response time may call for viewing a modern many-core architecture as a distributed system. In this view, the cores replicate shared data and ensure consistency amo ...

ACM Press2014

A Versatile 1.4-mW 6-bits CMOS ADC for Pulse-Based UWB Communication Systems

Pierre-André Farine, Cyril Botteron, Christian Robert, Frédéric Chastellain, Saeed Ghamari

An Analog to Digital Converter (ADC) using the low duty-cycle nature of pulse-based Ultra Wide-Band (UWB) communications to reduce its power consumption is proposed. Implemented in CMOS 180 nm technology, it can capture a 5 ns window at 4 GS/s each 100 ns, ...

2014

A Unified Online Directed Acyclic Graph Flow Manager for Multicore Schedulers

David Atienza Alonso, Karim Kanoun

Numerous Directed-Acyclic Graph (DAG) schedulers have been developed to improve the energy efficiency of various multi-core systems. However, the DAG monitoring modules proposed by these schedulers make a priori assumptions about the workload and relations ...

IEEE2014

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

Boris Robert Grot

As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and route ...

Institute of Electrical and Electronics Engineers2014

FRP-balsa composite sandwich bridge deck with complex core configuration

Thomas Keller, Anastasios Vassilopoulos, Julia De Castro San Roman Fest, Michael Osei-Antwi

The aim of this work was to investigate to what extent the performance of a glass fiberreinforced polymer (GFRP) sandwich slab-bridge with uniform high-density balsa core could be improved in terms of structural efficiency and weight thanks to a more compl ...

2014

Everything You Always Wanted to Know about Synchronization but Were Afraid to Ask

Rachid Guerraoui, Vasileios Trigonakis, Tudor Alexandru David

This paper presents the most exhaustive study of synchronization to date. We span multiple layers, from hardware cache-coherence protocols up to high-level concurrent software. We do so on different types of architectures, from single-socket - uniform and ...

2013

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

Pascal Frossard, David Atienza Alonso, Karim Kanoun

We consider the problem of energy-efficient on-line scheduling for slice-parallel video decoders on multicore systems. We assume that each of the processors are Dynamic Voltage Frequency Scaling (DVFS) enabled such that they can independently trade off per ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Design and Production of the ECCOFLOW Resistive Fault Current Limiter

Bertrand Dutoit

The European project ECCOFLOW aims at a versatile resistive-type superconducting fault current limiter. For the first time, such a device will be tested at two different sites. The project partners have developed a superconducting fault current limiter des ...

Institute of Electrical and Electronics Engineers2013

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate clocking for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC sta ...

2013

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Semiconductor intellectual property core

Consensus inside

A Versatile 1.4-mW 6-bits CMOS ADC for Pulse-Based UWB Communication Systems

A Unified Online Directed Acyclic Graph Flow Manager for Multicore Schedulers

A Unified Online Directed Acyclic Graph Flow Manager for Multicore Schedulers

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

FRP-balsa composite sandwich bridge deck with complex core configuration

Everything You Always Wanted to Know about Synchronization but Were Afraid to Ask

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

Design and Production of the ECCOFLOW Resistive Fault Current Limiter

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Graph Chatbot

Chattez avec Graph Search

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Everything You Always Wanted to Know about Synchronization but Were Afraid to Ask

A Unified Online Directed Acyclic Graph Flow Manager for Multicore Schedulers

Consensus inside

A Versatile 1.4-mW 6-bits CMOS ADC for Pulse-Based UWB Communication Systems

FRP-balsa composite sandwich bridge deck with complex core configuration

Design and Production of the ECCOFLOW Resistive Fault Current Limiter

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

A Unified Online Directed Acyclic Graph Flow Manager for Multicore Schedulers