Concept

VDSL

Publications associées (33)

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Volkan Cevher, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Kiarash Gharibdoust

Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends h ...

EPFL2016

Architectural Modeling of a Multi-Tone/Single-Sideband Serial Link Transceiver for Lossy Wireline Data Links

Yusuf Leblebici, Gain Kim

This paper presents a serial link transceiver (TRX) architecture that enables high-speed data transmission over a lossy backplane channel without the presence of equalization circuits. The proposed architecture employs multi-tone signaling to reduce inter- ...

Ieee2016

A Poisson Hidden Markov Model for Multiview Video Traffic

Pascal Frossard, Lorenzo Rossi

Multiview video has recently emerged as a means to improve user experience in novel multimedia services. We propose a new stochastic model to characterize the traffic generated by a Multiview Video Coding (MVC) variable bit-rate source. To this aim, we res ...

2015

Forge: Generating a High Performance DSL Implementation from a Declarative Specification

Martin Odersky, Tiark Rompf

Domain-specific languages provide a promising path to automatically compile high-level code to parallel, heterogeneous, and distributed hardware. However, in practice high performance DSLs still require considerable software expertise to develop and force ...

Assoc Computing Machinery2014

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology

Mohammad Amin Shokrollahi, Christoph Walter, Harm Cronie, Anant Pratap Singh, Klaas Lammert Hofstra, Kia Salimi

The continuing demand for higher bandwidth in serial interconnects has pushed the symbol rate of differential lanes into the high-insertion-loss region of channels. Multi-level signaling such as differential PAM-4 [1] has been used to mitigate the loss of ...

2014

A Distributed Video Coding System for Multi View Video Plus Depth

Thomas Maugey

Multi-view video plus depth (MVD) is gathering huge attention, as witnessed by the recent standardization activity, since its rich information about the geometry of the scene allows high-quality synthesis of virtual viewpoints. Distributed video coding of ...

2013

System design of a 24 GHz phased-array front-end for low-power applications

Pierre-André Farine, Cyril Botteron, Gabriele Tasselli, Ban Wang

This paper deals with the design of a 4-channel phased-array receiver Front-End (FE) architecture working at 24 GHz. Targeting low power applications such as radar sensors and medium bit-rate transceivers, a local oscillator shifting architecture is propos ...

2012

Identification and Analysis of Queue Spillovers in City Street Networks

Nikolaos Geroliminis

We propose a methodology for identifying queue spillovers in city street networks with signalized intersections using data from conventional surveillance systems, such as counts and occupancy from loop detectors. The key idea of the proposed methodology is ...

2011

Achieving Linear Scaling with Interference Alignment

Ayfer Özgür Aydin

Recent results have shown that interference alignment can achieve K/2 degrees of freedom in a K-user interference channel with time or frequency varying channel coefficients. For fixed number of users K, the number of degrees of freedom characterizes the a ...

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