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In this paper, we make the case for building high-performance asymmetric-cell caches (ACCs) that employ recently-proposed asymmetric SRAMs to reduce leakage proportionally to the number of resident zero bits. Because ACCs target memory value content (indep ...
An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a ...
High-performance caches statically pull up the bit-lines in all cache subarrays to optimize cache access latency. Unfortunately, such architecture results in a significant waste of energy in nanoscale CMOS implementations due to high leakage and bitline di ...
SPAD (single-photon avalanche diode) arrays are single-photon imagers that can provide unparalleled timeresolved sensing performance. Since their inception in standard CMOS technologies (2003), a host of architectures and target applications have been expl ...
We revisit the idea of using small line buffers in-front of caches. We propose ReCast, a tiny tag set cache that filters a significant number of tag probes to the L2 tag array thus reducing power. The key contribution in ReCast is S-Shift, a simple indexin ...
In this paper we propose a new method for rendering crowds of virtual humans with dynamicallydeformed skeletons with levels of detail using two simple caching schemes for animations and geometry. Weshow how the virtual heritage project ERATO pushed for the ...
