Publications associées à Porte logique

Controlling charge-transfer at the gate interface of organic field-effect transistors

The performance and charge transport characteristics of pentacene transistors with oxide gates such as SiO2 and Al2O3 have been recently shown to largely depend on the density of residual carriers due to electron acceptor defects at the oxide surface. The ...

2008

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching ...

2008

KFM detection of quantified charges injected into a thin SiO2 layer containing Si nps embedded by ultra low energy ion implantation using stencil lithography

Jürgen Brugger, Andreea Veronica Savu, Marc Antonius Friedrich van den Boogaart

Non volatile flash memories based on nanoparticles (nps) are one of the identified routes to a further downscaling of future CMOS technology. New features such as Coulomb blockade and quantized charging effects can appear at room temperature only for a lim ...

2008

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

The increasing importance,of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the rece ...

2008

Programmable Logic Circuits based on Ambipolar CNFET

Giovanni De Micheli, David Atienza Alonso, Yusuf Leblebici, Mohamed Haykel Ben Jamaa

Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PLA) can be built out of these devices, and we illustrate how they outperform u ...

2008

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

Seyed Armin Tajalli, Yusuf Leblebici

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach ha ...

IEEE2008

Abrupt current switching due to impact ionization effects in Ω-MOSFET on low doped bulk silicon

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott

In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Ω-MOSFET). The Ω-MOSFETs are fabricated on low-doped (8×1014cm-3) bulk silicon by bulk silicon ...

2008

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Giovanni De Micheli, David Atienza Alonso

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems on Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...

2008

Compact Modeling of Suspended Gate FET

Mihai Adrian Ionescu, Michel Declercq, Dimitrios Tsamados, Yogesh Singh Chauhan, Nicolas Abelé, Christoph Eggimann

For the first time, a compact model for suspended gate (SG) FET valid for entire bias range is proposed. The model is capable of simulating both pull-in and pull-out effects, which are the two important phenomena of this device. A novel hybrid numerical si ...

2008

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Porte logique

Controlling charge-transfer at the gate interface of organic field-effect transistors

MOS current-mode logic standard cells for high-speed low-noise applications

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

KFM detection of quantified charges injected into a thin SiO2 layer containing Si nps embedded by ultra low energy ion implantation using stencil lithography

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

Programmable Logic Circuits based on Ambipolar CNFET

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

Abrupt current switching due to impact ionization effects in Ω-MOSFET on low doped bulk silicon

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Compact Modeling of Suspended Gate FET

Graph Chatbot

Chattez avec Graph Search

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Controlling charge-transfer at the gate interface of organic field-effect transistors

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

MOS current-mode logic standard cells for high-speed low-noise applications

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

KFM detection of quantified charges injected into a thin SiO2 layer containing Si nps embedded by ultra low energy ion implantation using stencil lithography

Programmable Logic Circuits based on Ambipolar CNFET

Abrupt current switching due to impact ionization effects in Ω-MOSFET on low doped bulk silicon

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

Compact Modeling of Suspended Gate FET