Concept

Test de performance

Publications associées (108)

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Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed varia ...

2007

STMBench7: A Benchmark for Software Transactional Memory

Rachid Guerraoui, Michal Kapalka

Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse-grained locking and easier to use than fine-grained locking. However, STM im ...

2007

Scheduling threads for constructive cache sharing on CMPs

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of offchip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlappi ...

2007

Generic and Systematic Evaluation of Haptic Interfaces Based on Testbeds

Hannes Bleuler, Fei Wang, Evren Samur

The purpose of evaluation procedures is to achieve both qualitative and quantitative statements on haptic rendering realism and performance. Since a haptic interface provides an interaction between a user and a virtual environment, fidelity of a haptic int ...

IEEE2007

Using speed diagrams for symbolic quality management

Joseph Sifakis

We present a quality management method for multimedia applications. The method takes as input an application software composed of actions. The execution times of actions are unknown increasing functions of quality level parameters. The method allows the co ...

2007

Statistical sampling of microarchitecture simulation

Babak Falsafi

Current software-based micro architecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often in ...

2006

Parallel depth first vs. work stealing schedulers on CMP architectures

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of off-chip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlapp ...

2006

Simulation sampling with live-points

Babak Falsafi

Current simulation-sampling techniques construct accurate model state for each measurement by continuously warming large microarchitectural structures (e.g., caches and the branch predictor) while functionally simulating the billions of instructions betwee ...

2006

Analysis of peer-to-peer file dissemination

Jochen Mundinger

In recent years, overlay networks have proven a popular way of disseminating potentially large files from a single server S to a potentially large group of N end users via the Internet. A number of algorithms and protocols have been suggested, implemented ...

2006

A field investigation of the intermediate light switching by users

David Lindelöf, Nicolas Morel

This paper describes how data collected during a continuously running data acquisition program on the LESO building in Lausanne, Switzerland, was used to measure the intermediate light switch probability by users as a function of current illuminance levels ...

2006