Concept

MOS Technology 6502

Publications associées (48)

Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

Elmira Shahrabi, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Mahmoud Hadad, Behnoush Attarimashalkoubeh

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180 nm CMOS technology chips. The proposed integration method enables low- cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory sy ...

Ieee2016

Observation of Ultrafast Free Carrier Dynamics in Single Layer MoS2

Marco Grioni, Jens Christian Johannsen

The dynamics of excited electrons and holes in single layer (SL) MoS2 have so far been difficult to disentangle from the excitons that dominate the optical response of this material. Here, we use time- and angle-resolved photoemission spectroscopy for a SL ...

Amer Chemical Soc2015

Multi-Gigabyte On-Chip DRAM Caches for Servers

Dorde Jevdic

While DRAM latency has long been recognized as a major bottleneck in servers, DRAM bandwidth is emerging as an important bottleneck as server processors shift to many-core architectures to allow for sustainable throughput improvements. The rapid expansion ...

EPFL2015

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

Pierre-André Farine, Rafal Tomasz Dlugosz

The paper presents a new initialization mechanism based on a Convex Combination Method (CCM) for Kohonen self-organizing Neural Networks (NNs) realized in the CMOS technology. A proper selection of initial values of the neuron weights exhibits a strong imp ...

Elsevier Science Inc2015

A Low Dark Count p-i-n Diode Based SPAD in CMOS Technology

Edoardo Charbon

In this paper, a novel CMOS single-photon avalanche diode (SPAD) is presented, and the device is designed using a vertical p-i-n diode construction. The p-i-n diode with a wide depletion region enables a low-noise operation. The proposed design achieves da ...

2015

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

Adam Shmuel Teman

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process ...

Institute of Electrical and Electronics Engineers2014

Design of Digital SoC for Operation at High Temperatures

Radisav Cojbasic

There is a growing demand for Systems-on-Chip, integrating microprocessors, on-chip memories, data converters and a variety of sensors, which are capable of reliable operation at high temperatures. For instance, modern aircraft industry demands microcontro ...

EPFL2014

FireBird: PowerPC e200 Based SoC for High Temperature Operation

Andreas Peter Burg, Yusuf Leblebici, Thomas Maeder, Pascal Andreas Meinerzhagen, Conor Joseph Slater, Ömer Cogal, Carl Christian Sten Dominic Senning, Radisav Cojbasic

PowerPC Architecture microcontrollers are commonly used in embedded applications. In this work we present FireBird, the first PowerPC based SoC for reliable operation beyond 200C. It is a significant challenge to design SoCs for reliable operation at high ...

2013

Offset Compensation Based on Distributed Hall Cell Architecture

Pierre-André Farine, Pavel Kejik, Pierre-François Thibault Bourdelle

A new offset reduction strategy for CMOS Hall devices is proposed. The novelty is to fragment the Hall device into multiple Hall blocks, distributed over the silicon area and easy to interconnect. The suitable number of Hall blocks and the bias current lev ...

Institute of Electrical and Electronics Engineers2013

Carbon Nanotube Precise Assembly for CMOS and NEMS Applications

Ji Cao

As complementary metal–oxide–semiconductor (CMOS) scaling meets fundamental limitations, revolutionary device concepts and materials are urgently needed as alternatives or supplements to CMOS technology. Carbon nanotubes (CNTs), featuring extraordinary phy ...

EPFL2013

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