Récupération de données

vignette|Un laboratoire de récupération de données La récupération de données (ou restauration de données) est une opération informatique qui consiste à retrouver les données perdues à la suite d'une erreur humaine, une défaillance matérielle, une défaillance logicielle d'un programme ou d'un système d'exploitation, un accident ou au moment opportun d'un test de récupération de données défini dans une procédure de stratégie de sauvegarde et d'archive (également appelé plan de sauvegarde). La difficulté de la restauration de donnée varie beaucoup, pouvant être une simple formalité ou au contraire, un défi technologique. Des logiciels spécifiques existent et plusieurs entreprises se spécialisent dans le domaine. Contexte Les scénarios de récupération de données les plus courants impliquent une défaillance du système d'exploitation, un dysfonctionnement d'un périphérique de stockage, une défaillance logique des périphériques de stockage, des dommages accidentels, une suppressi

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output (I/O) interfaces is subject to much slower growth, due to the limited number of packaging pins and the intrinsic bandwidth constraint of electrical parallel buses. While upcoming serial interfaces provide some relief to this problem in the short term, their data rates remain subject to the inherent bandwidth-distance trade-off in electrical data links. A major move to an optical data link paradigm for very short-distance (board-to-board and chip-to-chip) communications would allow for considerable I/O interface bandwidth enhancement, but this solution currently lacks economic success. Today's optical receivers indeed use compound semiconductor photodetectors in combination with bipolar or BiCMOS amplifiers and CMOS clock and data recovery circuits. The move to fully integrated silicon CMOS receivers would contribute to cost reduction in several ways. Monolithic integration is not only mandatory for optical receivers to become a true I/O interface, it also results in lower volume manufacturing cost, improved yield and reduced assembly and test expenses. The presented work deals with the general problem of monolithic integration and shows the feasibility of fully integrated multi-channel CMOS-compatible fiber-optic receivers for short-distance communications. Multiple challenges, related to the limitations of high-performance analog design in advanced CMOS processes, as well as the combination with a novel silicon photodetector, are addressed. An important realization in this context is that complete integration of the receiver allows for a system-level (global) optimization approach of all components. In this context, we introduce a top-down design methodology propagating the system-level receiver specifications down to the block level, then to the transistor-level. Based on these specifications, transimpedance and limiting amplifier designs are proposed. The limiting amplifier in particular has been designed according to a scaling method for area and power optimization. Magnetic inter-channel coupling effects in multi-channel receivers with inductive peaking have been analyzed, both in theory and by measurement. The clock and data recovery circuit is based on a compact gated oscillator topology and achieves low power and area through partial resource sharing. As this particular topology is not conventionally used for such applications, a novel modeling and verification approach based on statistical and behavioral simulation is proposed. This methodology allows to determine the required power consumption for given jitter specifications and thus results in a power-optimized design. A low-power low-area gated-oscillator clock recovery circuit has been implemented to verify the presented methodology. In summary, a global top-down approach to the design of fiber-optic receivers is presented. Operation of all building blocks at or above the targeted per channel data rate of 2.5Gb/s shows the feasibility of monolithically integrated multi-channel optical receivers in standard CMOS technologies.

EPFL2006

Linear Recursive State Estimation of Hybrid and Unbalanced AC/DC Micro-Grids using Synchronized Measurements

Willem Lambrichts, Mario Paolone

In this paper, we present an exact (i.e. non-approximated) and linear measurement model for hybrid AC/DC micro-grids for recursive state estimation (SE). More specifically, an exact linear model of a voltage source converter (VSC) is proposed. It relies on the complex VSC modulation index to relate the quantities at the converters DC side to the phasors at the AC side. The VSC model is derived from a transformer-like representation and accounts for the VSC conduction and switching losses. In the case of three-phase unbalanced grids, the measurement model is extended using the symmetrical component decomposition where each sequence individually affects the DC quantities. Synchronized measurements are provided by phasor measurement units and DC measurement units in the DC system. To make the SE more resilient to vive step changes in the grid states, an adaptive Kalman Filter that uses an approximation of the prediction-error covariance estimation method is proposed. This approximation reduces the computational speed significantly with only a limited reduction in the SE performance. The hybrid SE is validated in an EMTP-RV time-domain simulation of the CIGRE AC benchmark micro-grid that is connected to a DC grid using 4 VSCs. Bad data detection and identification using the largest normalised residual is assessed with respect to such a system. Furthermore, the proposed method is compared with a non-linear weighted least squares SE in terms of accuracy and computational time.

2022

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

EPFL2006

The efficiency of DNA extraction kit and the efficiency of recovery techniques to release DNA using flow cytometry

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Linear Recursive State Estimation of Hybrid and Unbalanced AC/DC Micro-Grids using Synchronized Measurements

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

The efficiency of DNA extraction kit and the efficiency of recovery techniques to release DNA using flow cytometry

Linear Recursive State Estimation of Hybrid and Unbalanced AC/DC Micro-Grids using Synchronized Measurements