Concept

Manycore processor

Publications associées (259)

Parallel eigenvalue reordering in real Schur forms

A parallel algorithm for reordering the eigenvalues in the real Schur form of a matrix is presented and discussed. Our novel approach adopts computational windows and delays multiple outside-window updates until each window has been completely reordered lo ...

2009

TMunit: Testing Transactional Memories

Vincent Gramoli, Pascal Felber

Transactional memory (TM) is expected to become a widely used parallel programming paradigm for multi-core architectures. To reach this goal, we need tools that do not only help develop TMs, but also test them and evaluate them on a wide range of workloads ...

2009

Concurrent Programming Paradigms, A Comparison in Scala

Rachid Guerraoui, Martin Odersky, Mohsen Lesani

There is a rapid rise of multi-cores in recent hardware architectures. To exploit computational power of multi-core architectures, software should shift to be as concurrent as possible; and therefore should have concurrency control mechanisms. There are di ...

2009

Performance prediction and race detection in message-passing parallel applications

Basile Schäli

The combination of low cost clusters and multicore processors lowers the barrier for accessing massive amounts of computing power. As computational sciences advance, the use of in silico simulations to complement in vivo experiments promises parallel progr ...

EPFL2009

Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last- level cache for multicore processors. The large working sets favor a shared cache design that maximizes the ag ...

2009

An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

Marco Mattavelli, Christophe Lucarz, Ghislain Roquier

The possibility of specifying both SW and HW components using the same language is a very attractive design approach. However, despite the efforts spent for implementing such approach using common programming languages such as C and C++, it has not yet sho ...

IEEE2009

Shore-MT: A Scalable Storage Manager for the Multicore Era

Anastasia Ailamaki, Babak Falsafi, Frederick Ryan Johnson, Ippokratis Pandis

Database storage managers have long been able to efficiently handle multiple concurrent requests. Until recently, however, a computer contained only a few single-core CPUs, and therefore only a few transactions could simultaneously access the storage manag ...

ACM2009

Optimal Multi-Processor SoC Thermal Simulation via Adaptive Differential Equation Solvers

Giovanni De Micheli, David Atienza Alonso, Ayse Kivilcim Coskun, Francesco Zanini

Thermal management is a critical challenge in the design of high performance multi-processor system-on-chips (MPSoCs). Therefore, accurate and fast thermal modeling tools are necessary for efficiently analyzing the thermal profiles of MPSoCs. This paper ad ...

IEEE/IFIP Press2009

Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip

David Atienza Alonso

Technology scaling imposes an ever increasing temperature stress on digital circuit design due to transistor density, especially on highly integrated systems, such as Multi- Processor Systems-on-Chip (MPSoCs). Therefore, temperature-aware design is mandato ...

IEEE Computer Society2009

Robustness and evolution in oscillatory systems with feedback loops

Marc Hafner

Feedback loops are major components of biochemical systems. Many systems show multiple such (positive or negative) feedback loops. Nevertheless, very few quantitative analyses address the question how such multiple feedback loops evolved. Based on publishe ...

2009

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