Calculateur analogique | EPFL Graph Search

thumb|L'Elwat, un calculateur analogique polonais fabriqué entre 1967 et 1969 ; les éléments visibles sont, de gauche à droite, un voltmètre, un téléscripteur, un oscilloscope et l'ordinateur à proprement parler. Un calculateur analogique est une application particulière des méthodes analogiques consistant à remplacer l'étude d'un système physique donné par celle d'un autre système physique régi par les mêmes équations. Pour que cela présente un intérêt, le système « analogue » doit être facile à construire, les mesures aisées et moins coûteuses que sur le système réel. Un calculateur analogique proprement dit est constitué d'un ensemble de modules électroniques (et/ou électromécaniques) interconnectés pour modéliser un problème à résoudre. Les connexions sont assurées par un panneau de câblage amovible facilitant les changements de problèmes. Les résultats (mesure des tensions électriques représentant les différentes variables) sont le plus souvent enregistrés sous forme de courbe

Analog microelectronic emulation for dynamic power system computation

Ira Nagel

Power system dynamic simulators can be classified according to multiple criteria, including speed, precision, cost and modularity (topology, characteristics and model). Existing simulators are based on time-consuming numeric algorithms, which provide very precise results. But the evolution of the power grid constantly changes the requirements for simulators. In fact, power consumption is steadily increasing; therefore, the power system is always operating closer to its limits. Moreover, focus is put on decentralized and stochastic green energy sources, leading to a much more complex and less predictable power system. In order to guarantee security of supply under these conditions, real-time control and online security assessment are of the utmost importance. The main requirement for power system simulators in this context thus becomes the simulation time. The simulator has to be able to reproduce power system phenomena much faster than their real-time duration. An effective way to accelerate computation time of power system stability simulators is based on analog emulation of the power system grid. The idea is to avoid the heavy, time-consuming numerical matrix calculations of the grid by using an instantaneous analog Kirchhoff grid, with which computation becomes intrinsically parallel and the simulation time independent of the power system topology size. An overview of the power system computation history and the evolution of microelectronics highlights that the renaissance of dedicated analog computation is justified. Modern VLSI technologies can overcome the drawbacks which caused the disappearance of analog computation units in the 1960s. This work addresses therefore the development of a power system emulation approach from its theoretical principles to the behavioral design and the microelectronic implementation of a first demonstrator. The approach used in this research is called AC emulation approach and is based on a one-to-one mapping of components of the real power system (generator, load and transmission line) by emulating their behavior on a CMOS microelectronic integrated circuit (ASIC). The signals propagating on the emulated grid are the shrunk and downscaled current and voltage waves of the real power system. The uniqueness of this emulation approach is that frequency dependence of the signals is preserved. Therefore, the range of phenomena that can be emulated with an AC emulator depends only on the implemented models. Within the framework of this thesis, we restrict our developments to transient stability analysis, as our main focus is put on emulation speed. v We provide behavioral AC emulation models for the three main power system components. Thereby, special attention is paid to the generator model, which is shown to introduce a systematic error. This error is analyzed and reduced by model adaptation. Behavioral simulation results validate the developed models. Moreover, we suggest custom programmable analog building blocks for the implementation of the proposed behavioral models. During their design, application specific requirements, as well as imperfections, calibration, mismatch and process-variation aspects, are taken into account. In particular, the design of the tunable floating inductance used in all three AC emulation models is discussed in detail. In fact, major design challenges have to be addressed in order to achieve an inductance suitable for our application. Finally, a first AC emulation demonstrator is presented. A benchmark using a fixed two- machine topology has been implemented using a 0.35μm 3.3V CMOS technology. The characteristics of the emulated components (i.e. generators and transmission lines) are reprogrammable, allowing short circuits to be emulated at different distances from the generator. The emulated phenomena are shown to be 10′000 times faster than real time, therefore proving the high-speed capabilities of AC emulation.

EPFL2013

Structured analog CMOS design based on the device inversion level

Danica Stefanovic

Standard analog design procedure is usually based on a large number of simulations, strongly depends on the type of analog circuit that has to be implemented and requires a lot of manipulation at the transistor level. Simulators offer accurate modeling and precise calculations, but on the other hand ascertaining circuit parameter dependences is difficult and depends on analog designer expertise and knowledge. Moreover, with CMOS technology improvements, the complexity of analog design tasks further increases, since the design specifications become more severe in terms of gain and speed, requiring at the same time minimization of the circuit surface. In this thesis, we propose a structured design approach that allowed us to simplify complex analog design problems and develop a global design strategy that can be used for the design of different analog cells. The basic concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The basic analog structure specifications are derived from circuit-level requirements, and its sizing in the environment imposed by the circuit demands less effort. Furthermore, the procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The transistor-level design procedure is based on the continuous MOS modeling approach and relies on the device inversion level as a fundamental design variable. Since all important design parameters can be expressed as continuous functions of the device inversion level, the design optimum as well as the technology limits can be easily found. Finally, the proposed design procedure is implemented as a CAD tool that guides and assists the user during analog design tasks and provides an interactive interface that allows instantaneous visualization of design trade-offs. At the same time, the user has a great degree of freedom in decision making which enables high human interactivity and design optimization.

EPFL2007

Multi-unit global energy management and optimization for network-on-chip applications

Zeynep Toprak Deniz

The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The significance of the problem is underlined by the increasing prominence of multi-core systems that must operate under strict power/energy budget constraints, both in mobile applications and in cases where special cooling arrangements can be very expensive. A range of solutions have been proposed over the last few years, which are mostly based on static, off-line calculation of a limited set of operating points in the form of optimum voltage and frequency assignments, that are subsequently chosen according to actual demands. Still, to our best knowledge, none of these studies have demonstrated an on-line solution to complex, multi-variable energy optimization problem which allows dynamic adjustment of individual operating frequencies and supply voltages of multiple processing elements. This thesis presents the design and silicon implementation of an analog-based energy optimizer unit, which is capable of dynamically adjusting power supply and clock frequencies of multiple embedded cores, tailored to the instantaneous workload information (computational task) and fully adaptive to variations in process and temperature. Our approach borrows from the basic principles of analog computation to continuously optimize the system-wide energy dissipation of multiple processing elements, converging on the global minima of the constrained optimization problem which are represented as stable operating points of a simple feedback loop. It is already well known that stable, approximate solutions of multi-variable optimization problems (such as gradient descent) can be obtained by using very compact analog circuits, e.g. resistive networks. The analogy between the energy minimization problem under timing constraints in a general task graph and the power minimization problem under Kirchhoff's current law constraints in an equivalent resistive network is exploited. The implementation of the on-line analog optimizer is then discussed. The realization of the blocks composing the system architecture is described, and circuit design issues are studied thoroughly. The three-loop demonstrator circuit of the proposed analog optimizer architecture has been implemented using a 0.18μm standard digital CMOS process. The overall circuit area of the optimizer is (245μm × 650μm) excluding decoupling capacitors, while each loop circuit occupies only (180μm × 120μm). Operating at a nominal supply of 1.8 V, the circuit is capable of supporting the desired frequency range of 170 MHz - 290 MHz, as well as the voltage range of 1.2 V - 1.8 V. Estimated workload levels for each task (loop) are provided as 4-bit binary inputs, and the corresponding solution for minimum energy consumption is observed as assigned supply voltages and operating frequencies for each processing element, for a certain task duration. The measured worst-case settling time for supply voltages is less than 50μs. The average power consumption of the entire three-loop optimizer is 4mW. Measurements experimentally validate the concept of fully analog, current-based solution to implement on-line energy minimization in complex multi-core systems under varying workload conditions. Key functional blocks of the proposed circuit operate in weak inversion, resulting in very low power dissipation for the optimizer. The prototype successfully demonstrates that the proposed optimizer block is also capable of taking into account the on-chip variations of temperature as well as process parameters. As such, it can be used as a generic building block for on-line energy optimization in complex systems.

EPFL2006