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Publications associées (181)

Plucking Motions for Tea Harvesting Robots Using Probabilistic Movement Primitives

This study proposes a harvesting robot capable of plucking tea leaves without cutting them with blades. To harvest high-quality tea, it is necessary to reproduce the plucking motion of breaking the petiole of the leaf, that is, the complicated human hand m ...

2020

Closing Leaks: Routing Against Crosstalk Side-Channel Attacks

Mirjana Stojilovic, Seyedeh Sharareh Mirzargar, Zeinab Seifoori

This paper presents an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some I ...

2020

Six additional replies - one more chorus of the S3 ballad

Dominique Foray

This paper has been written as a response to 'Six additional questions about smart specialization: implications for regional innovation policy 4.0' by M. Benner. The paper starts with the argument that recent academic work has enabled considerable progress ...

ROUTLEDGE JOURNALS, TAYLOR & FRANCIS LTD2020

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC

Andreas Peter Burg, David Ruffieux

In this paper, we describe a systematic low-power design methodology for technologies that offer a strong body factor. Specifically, we explore both the body bias voltage and the supply voltage knobs in order to find the MEP (minimum energy point) for a co ...

IEEE2019

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Felix Schürmann, James Gonzalo King, Michael Lee Hines, Pramod Shivaji Kumbhar, Aleksandr Ovcharenko, Jérémy Pierre Benoit Fouriaux

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually ...

2019

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

Andreas Peter Burg, David Ruffieux

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. W ...

IEEE2019

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Boris Robert Grot, Siddharth Gupta

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

IEEE2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

Wearable Sensors for Frequency-Multiplexed EIT and Multilead ECG Data Acquisition

Josias Basil Wacker, Fabian Braun, Michaël Rapin

This paper presents a wearable sensor architecture for frequency-multiplexed electrical impedance tomography (EIT) and synchronous multilead electrocardiogram (ECG) data acquisition. The system is based on a novel electronic sensing architecture, called co ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

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