Publications associées à Gestion de mémoire par régions

Comprehensive Memory Safety Validation: An Alternative Approach to Memory Safety

Comprehensive memory safety validation identifies the memory objects whose accesses provably comply with all classes of memory safety, protecting them from memory errors elsewhere at low overhead. We assess the breadth and depth of comprehensive memory saf ...

Ieee Computer Soc2024

Formal Foundations of Capture Tracking

Aleksander Slawomir Boruch-Gruszecki

Type systems are a device for verifying properties of programs without running them. Many programming languages used in the industry have always had a type system, while others were initially created without a type system and later adopted one, when the ad ...

EPFL2024

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

Anastasia Ailamaki, Periklis Chrysogelos, Angelos Christos Anadiotis, Syed Mohammad Aunn Raza

Most modern in-memory online transaction processing (OLTP) engines rely on multi-version concurrency control (MVCC) to provide data consistency guarantees in the presence of conflicting data accesses. MVCC improves concurrency by generating a new version o ...

ACM2023

ExG Signal Feature Selection Using Hyperdimensional Computing Encoding

David Atienza Alonso, Tomas Teijeiro Campo, Una Pale

Wearable IoT devices and novel continuous monitoring algorithms are essential components of the healthcare transition from reactive interventions focused on symptom treatment to more proactive prevention, from one-size-fits-all to personalized medicine, an ...

IEEE2022

Preventing Use-After-Free Attacks with Fast Forward Allocation

Sanidhya Kashyap, Jungwon Lim

Memory-unsafe languages are widely used to implement critical systems like kernels and browsers, leading to thousands of memory safety issues every year. A use-after-free bug is a temporal memory error where the program accidentally visits a freed memory l ...

USENIX ASSOC2021

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Robert Giterman

Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Verifying Software Network Functions with No Verification Expertise

George Candea, Solal Vincenzo Pirelli, Rishabh Ramesh Iyer, Luis David Figueiredo Mascarenhas Moreira Pedrosa, Matteo Rizzo

We present the design and implementation of Vigor, a software stack and toolchain for building and running software network middleboxes that are guaranteed to be correct, while preserving competitive performance and developer productivity. Developers write ...

ACM2019

Detailed Heap Profiling

James Richard Larus, Stuart Anthony Byma

Modern software systems heavily use the memory heap. As systems grow more complex and compute with increasing amounts of data, it can be difficult for developers to understand how their programs actually use the bytes that they allocate on the heap and whe ...

ACM2018

Detailed heap profiling

James Richard Larus, Stuart Anthony Byma

ACM2018

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Gestion de mémoire par régions

Comprehensive Memory Safety Validation: An Alternative Approach to Memory Safety

Formal Foundations of Capture Tracking

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

ExG Signal Feature Selection Using Hyperdimensional Computing Encoding

Preventing Use-After-Free Attacks with Fast Forward Allocation

Formal Verification of Rust with Stainless

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Verifying Software Network Functions with No Verification Expertise

Detailed Heap Profiling

Detailed heap profiling

Graph Chatbot

Chattez avec Graph Search

Comprehensive Memory Safety Validation: An Alternative Approach to Memory Safety

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

Preventing Use-After-Free Attacks with Fast Forward Allocation

ExG Signal Feature Selection Using Hyperdimensional Computing Encoding

Formal Foundations of Capture Tracking

Formal Verification of Rust with Stainless

Detailed heap profiling

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Verifying Software Network Functions with No Verification Expertise

Detailed Heap Profiling