Concept

Glossary of computer hardware terms

Publications associées (27)

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TRUSS: A Reliable, Scalable Server Architecture

Babak Falsafi

Traditional reliable servers require costly design changes to the processor, use custom system or application software, or cannot scale beyond a few processing elements. We present TRUSS, a family of server architectures providing reliable, scalable comput ...

2005

Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay

Babak Falsafi

Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in t ...

2002

Performance of CAP-specified linear algebra algorithms

Roger Hersch, Marc Mazzariol

The traditional approach to the parallelization of linear algebra algorithms such as matrix multiplication and LU factorization calls for static allocation of matrix blocks to processing elements (PEs). Such algorithms suffer from two drawbacks: they are v ...

Springer-Verlag1997

Computer-assisted generation of PVM/C++ programs using CAP

Roger Hersch

Parallelizing an algorithm consists of dividing the computation into a set of sequential operations, assigning the operations to threads, synchronizing the execution of threads, specifying the data transfer requirements between threads and mapping the thre ...

Springer-Verlag1996

Tempest and Typhoon: User-Level Shared Memory

James Richard Larus, David Wood

Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today’s machines limit these programs to a single communication paradigm, either message-passing or ...

ACM1994

The CHI, a new Fastbus interface and processor

Ken Hollingworth

The CERN Host Interface (CHI) is a family of interfaces to interconnect Fastbus, VMEbus, and external host computers. The Fastbus interface consists of a processor board (CHI-P) and host-specific I/O ports allowing connection using fast parallel or serial ...

1990

Sender-Based Message Logging

Willy Zwaenepoel

Sender-based message logging, a low-overhead mechanism for providing transparent fault-tolerance in distributed systems, is described. It differs from conventional message logging mechanisms in that each message is logged in volatile memory on the machine ...

1987