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Concept# Analog multiplier

Résumé

In electronics, an analog multiplier is a device that takes two analog signals and produces an output which is their product. Such circuits can be used to implement related functions such as squares (apply same signal to both inputs), and square roots.
An electronic analog multiplier can be called by several names, depending on the function it is used to serve (see analog multiplier applications).
Voltage-controlled amplifier versus analog multiplier
If one input of an analog multiplier is held at a steady-state voltage, a signal at the second input will be scaled in proportion to the level on the fixed input. In this case, the analog multiplier may be considered to be a voltage controlled amplifier. Obvious applications would be for electronic volume control and automatic gain control (AGC). Although analog multipliers are often used for such applications, voltage-controlled amplifiers are not necessarily true analog multipliers. For example, an integrated circuit desi

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EE-110: Logic systems (for MT)

Ce cours couvre les fondements des systèmes numériques. Sur la base d'algèbre Booléenne et de circuitscombinatoires et séquentiels incluant les machines d'états finis, les methodes d'analyse et de synthèse de systèmelogiques sont étudiées et appliquée

PHYS-405: Experimental methods in physics

The course's objectivs are: Learning several advenced methods in experimental physics, and critical reading of experimental papers.

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Standard analog design procedure is usually based on a large number of simulations, strongly depends on the type of analog circuit that has to be implemented and requires a lot of manipulation at the transistor level. Simulators offer accurate modeling and precise calculations, but on the other hand ascertaining circuit parameter dependences is difficult and depends on analog designer expertise and knowledge. Moreover, with CMOS technology improvements, the complexity of analog design tasks further increases, since the design specifications become more severe in terms of gain and speed, requiring at the same time minimization of the circuit surface. In this thesis, we propose a structured design approach that allowed us to simplify complex analog design problems and develop a global design strategy that can be used for the design of different analog cells. The basic concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The basic analog structure specifications are derived from circuit-level requirements, and its sizing in the environment imposed by the circuit demands less effort. Furthermore, the procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The transistor-level design procedure is based on the continuous MOS modeling approach and relies on the device inversion level as a fundamental design variable. Since all important design parameters can be expressed as continuous functions of the device inversion level, the design optimum as well as the technology limits can be easily found. Finally, the proposed design procedure is implemented as a CAD tool that guides and assists the user during analog design tasks and provides an interactive interface that allows instantaneous visualization of design trade-offs. At the same time, the user has a great degree of freedom in decision making which enables high human interactivity and design optimization.

Growing demand for the solid state meters for power and energy measurement leads to the fully integrated Hall sensor based microsystem solutions. In this paper we describe fully integrated SOI Hall sensor based microsystem for power and energy measurements with dynamic offset cancellation. Since Hall sensor behaves like a natural four quadrant multiplier it is used to multiply the line voltage and current giving the output voltage proportional to the instantaneous power. Furthermore, voltage at the Hall output is proportional to the line active power and can be further processed. By converting the sensor output voltage to digital signal using a sigma-delta demodulator followed by a digital filtering, the energy consumption is observed at the end of the processing chain. The entire microsystem has been designed for high linearity and resolution, and integrated in 0.5 mu m FD SOI process.

2004A novel analogue power-efficient 2-D programmable finite impulse response image filter is proposed. This solution is based on the current-mode Gilbert-vector-multiplier operating in the weak inversion region, which allows for ultra low power operation. The main advantage is in the asynchronous and parallel calculation of all pixel values without using any clock generator. The filter is a programmable structure that allows programmability of different filter masks both low-pass and high-pass. An experimental filter integrated circuit with a resolution of 6x1 pixels dissipates in measurements a power of 30 μW at a data rate of 30 kframes/s in a 180 nm CMOS technology. One of the intended applications of our proposed image filter is in data compression in wireless endoscopic capsules.