Êtes-vous un étudiant de l'EPFL à la recherche d'un projet de semestre?
Travaillez avec nous sur des projets en science des données et en visualisation, et déployez votre projet sous forme d'application sur Graph Search.
Concept
Oberon (operating system)
Résumé
The Oberon System is a modular, single-user, single-process, multitasking operating system written in the programming language Oberon. It was originally developed in the late 1980s at ETH Zurich. The Oberon System has an unconventional visual text user interface (TUI) instead of a conventional command-line interface (CLI) or graphical user interface (GUI). This TUI was very innovative in its time and influenced the design of the Acme text editor for the Plan 9 from Bell Labs operating system.
The latest version of the Oberon System, Project Oberon 2013, is still maintained by Niklaus Wirth and several collaborators, but older ETH versions of the system have been orphaned. The system also evolved into the multi-process, symmetric multiprocessing (SMP) capable A2 (formerly Active Object System (AOS), then Bluebottle), with a zooming user interface (ZUI).
The Oberon operating system was originally developed as part of the NS32032-based Ceres workstation project. It was written almost entirely (and in the 2013 version entirely is valid) in the Oberon programming language.
The basic system was designed and implemented by Niklaus Wirth and Jürg Gutknecht and its design and implementation is fully documented in their book "Project Oberon". The user Interface and programmers reference is found in Martin Reiser's book "The Oberon System". The Oberon System was later extended and ported to other hardware platforms
by a team at ETH Zurich and there was recognition in popular magazines.
Wirth and Gutknecht (although being active computer science professors) refer to themselves as 'part-time programmers' in the book Project Oberon. In late 2013, a few months before his 80th birthday, Wirth published a second edition of Project Oberon. It details implementing the Oberon System using a reduced instruction set computer (RISC) CPU of his own design realized on a Xilinx field-programmable gate array (FPGA) board. It was presented at the symposium organized for his 80th birthday at ETH Zurich. In the meantime, several emulators for this version were implemented.
Source officielle
À propos de ce résultat
Cette page est générée automatiquement et peut contenir des informations qui ne sont pas correctes, complètes, à jour ou pertinentes par rapport à votre recherche. Il en va de même pour toutes les autres pages de ce site. Veillez à vérifier les informations auprès des sources officielles de l'EPFL.