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Concept
EXPEED
Résumé
The Nikon Expeed /video processors (often styled EXPEED) are media processors for Nikon's digital cameras. They perform a large number of tasks: Bayer filtering, demosaicing, corrections/dark-frame subtraction, reduction, image sharpening, , gamma correction, image enhancement/Active D-Lighting, colorspace conversion, chroma subsampling, framerate conversion, /chromatic aberration correction, /JPEG encoding, video compression, display/video interface driving, , face detection, audio processing/compression/encoding and computer data storage/data transmission.
Expeed's multi-processor system on a chip solution integrates an image processor in multi-core processor architecture, with each single processor-core able to compute many instructions/operations in parallel. Storage and display interfaces and other modules are added and a digital signal processor (DSP) increases the number of simultaneous computations. An on-chip 32-bit microcontroller initiates and controls the operation and data transfers of all processors, modules and interfaces and can be seen as the main control unit of the camera.
In each generation Nikon uses different versions for its professional and consumer DSLRs / MILCs, whereas its compact cameras use totally different architectures. This is different from for example Canons DIGIC: its professional DSLRs double the processors of its consumer DSLR series. The Expeed is an application-specific integrated circuit (ASIC) built by Socionext specifically for Nikon designs according to Nikon specifications.
The Nikon Expeed is based on the Socionext Milbeaut imaging processors with 16-bit per pixel multi-core FR-V processor architecture, using a highly parallel pipelined architecture which allows efficient hardware use, increasing throughput and reducing power consumption. Each core uses an eight-way 256-bit very long instruction word (VLIW, MIMD) and is organized in a four-unit superscalar pipelined architecture (Integer (ALU)-, Floating-point- and two media-processor-units) giving a peak performance of up to 28 instructions per clock cycle and core.
Source officielle
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