Publications associées à Hardware emulation

Efficient Hardware Design Of Iterative Stencil Loops

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Ieee2016

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Paolo Ienne, Andrew James Becker, Ryan Charles Kastner, Wei Hu

Secure hardware design is a challenging task that goes far beyond ensuring functional correctness. Important design properties such as non-interference cannot be verified on functional circuit models due to the lack of essential information (e.g., sensitiv ...

Assoc Computing Machinery2016

Operation of a Concurrent Design Facility for university projects

Louis Antoine Masson, Anton Ivanov, Federico Belloni

Concurrent Design is a part of the systems engineering process, which has been widely adopted in space mission design. This paper describes the setting up a facility in a university and will try to answer a question of where the Concurrent Design Facility ...

IEEE2016

Design of Energy-Efficient Discrete Cosine Transform using Pruned Arithmetic Circuits

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

Inexact circuits and approximate computing have been gaining a lot of interest in order to improve performances and energy efficiency beyond the boundaries of conventional digital circuits. Image and video processing is one of the best candidate for applyi ...

IEEE2016

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Marco Mattavelli, Endri Bezati, Ab Al Hadi Bin Ab Rahman, Anatoly Prihozhy

This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are th ...

Ieee-Inst Electrical Electronics Engineers Inc2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, Barbara Jobstmann, David Novo Bruna, Andrew James Becker, Mohsen A A Ewaida

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Springer2015

Compressive image acquisition in modern CMOS IC design

Pierre Vandergheynst, Alexandre Schmid, Yusuf Leblebici, Mahdad Hosseini Kamal, Nikola Katic

Compressive sampling (CS) offers bandwidth, power, and memory size reduction compared to conventional (Nyquist) sampling. These are very attractive features for the design of modern complementary metal-oxide semiconductor (CMOS) image sensors, cameras, and ...

Wiley-Blackwell2015

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Hardware emulation

Efficient Hardware Design Of Iterative Stencil Loops

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Operation of a Concurrent Design Facility for university projects

Design of Energy-Efficient Discrete Cosine Transform using Pruned Arithmetic Circuits

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Accelerators for Data Processing

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Compressive image acquisition in modern CMOS IC design

Hardware and Algorithms for Ultrasonic Depth Imaging

Graph Chatbot

Chattez avec Graph Search

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Accelerators for Data Processing

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Operation of a Concurrent Design Facility for university projects

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Efficient Hardware Design Of Iterative Stencil Loops

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Design of Energy-Efficient Discrete Cosine Transform using Pruned Arithmetic Circuits

Compressive image acquisition in modern CMOS IC design

Hardware and Algorithms for Ultrasonic Depth Imaging