Publications associées à Mobile processor

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

Workflows in AiiDA: Engineering a high-throughput, event-based engine for robust and modular computational workflows

Nicola Marzari, Giovanni Pizzi, Martin Uhrin, Sebastiaan Philippe Huber

Over the last two decades, the field of computational science has seen a dramatic shift towards incorporating high-throughput computation and big-data analysis as fundamental pillars of the scientific discovery process. This has necessitated the developmen ...

2020

One Joule per GFlop for BLAS2 Now!

Vincent Keller

Energy consumption is today one of the major topics that the HPC community tries to tackle. In this paper, the authors present a thought experiment aiming at building a node of a supercomputer based on a GPU (Nvidia GTX280). The paper concentrate on BLAS2 ...

American Institute of Physics2010

ECC2K-130 on Cell CPUs

Joppe Willem Bos, Thorsten Kleinjung

This paper describes an implementation of Pollard's rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband Engine Architecture. Our implementation targets the elliptic curve discrete loga ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

PyNEST: a convenient interface to the NEST simulator

Eilif Benjamin Muller, Marc-Oliver Gewaltig

The neural simulation tool NEST (http://www.nest-initiative.org) is a simulator for heterogeneous networks of point neurons or neurons with a small number of compartments. It aims at simulations of large neural systems with more than 10^4 neurons and 10^7 ...

Frontiers Research Foundation2008

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Seyed Armin Tajalli, Paul Victor Georges Muller, Yusuf Leblebici

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient ...

2007