Publications associées à Hazard (computer architecture)

Practical considerations of diffusion-weighted MRS with ultra-strong diffusion gradients

IntroductionDiffusion-weighted magnetic resonance spectroscopy (DW-MRS) offers improved cellular specificity to microstructure-compared to water-based methods alone-but spatial resolution and SNR is severely reduced and slow-diffusing metabolites necessita ...

Frontiers Media Sa2023

Jointly Optimizing Sensing Pipelines for Multimodal Mixed Reality Interaction

Lakmal Buddika Meegahapola

Natural human interactions for Mixed Reality Applications are overwhelmingly multimodal: humans communicate intent and instructions via a combination of visual, aural and gestural cues. However, supporting low-latency and accurate comprehension of such mul ...

IEEE COMPUTER SOC2020

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

The Inherent Cost of Remembering Consistently

Rachid Guerraoui, Mihail Igor Zablotchi, Nachshon Cohen

Non-volatile memory (NVM) promises fast, byte-addressable and durable storage, with raw access latencies in the same order of magnitude as DRAM. But in order to take advantage of the durability of NVM, programmers need to design persistent objects which ma ...

2018

The Inherent Cost of Remembering Consistently

Rachid Guerraoui, Mihail Igor Zablotchi, Nachshon Cohen

Non-volatile memory (NVM) promises fast, byte-addressable and durable storage, with raw access latencies in the same order of magnitude as DRAM. But in order to take advantage of the durability of NVM, programmers need to design persistent objects which ma ...

2018

Optimized Memory Access For Dynamically Scheduled High Level Synthesis

Paolo Ienne, Atri Bhattacharyya

Dynamically-scheduled elastic circuits generated by High-Level Synthesis (HLS) tools are inherently out-of-order, following the flow of data rather than the evolution of an instruction pointer. Components of the circuit which access memory need to be conne ...

2018

Asynchronous memory access chaining

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber

In-memory databases rely on pointer-intensive data structures to quickly locate data in memory. A single lookup operation in such data structures often exhibits long-latency memory stalls due to dependent pointer dereferences. Hiding the memory latency by ...

2015

FIR filters for hardware-based real-time multi-band image blending

Yusuf Leblebici, Vladan Popovic

Creating panoramic images has become a popular feature in modern smart phones, tablets, and digital cameras. A user can create a 360 degree field-of-view photograph from only several images. Quality of the resulting image is related to the number of source ...

Spie-Int Soc Optical Engineering2015

A mixed-signal computer architecture and its application to power system problems

Theodoros Kyriakidis

Radical changes are taking place in the landscape of modern power systems. This massive shift in the way the system is designed and operated has been termed the advent of the ``smart grid''. One of its implications is a strong market pull for faster power ...

EPFL2015

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Sotiria Fytraki, Evangelos Vlachos

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu ...

2014