Concept

Hazard (computer architecture)

Publications associées (34)

A Map for Big Data Research in Digital Humanities

This article is an attempt to represent Big Data research in digital humanities as a structured research field. A division in three concentric areas of study is presented. Challenges in the first circle – focusing on the processing and interpretations of l ...

2015

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Sotiria Fytraki, Evangelos Vlachos

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu ...

2014

Architecture Internalisation in BIP

Joseph Sifakis, Simon Bliudze

Architectures allow shifting the focus of developers from low-level code to high-level structures ensuring coordination in component-based systems. If the architecture description language is expressive enough, it is possible to describe architectures in a ...

2014

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

OLTP in Wonderland -- Where do cache misses come from in major OLTP components?

Anastasia Ailamaki, Pinar Tözün

For several decades, online transaction processing has been one of the main applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Despite the novel approaches from industry an ...

ACM2013

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

Speculative Linearizability

Rachid Guerraoui, Viktor Kuncak, Giuliano Losa

Linearizability is a key design methodology for reasoning about implementations of concurrent abstract data types in both shared memory and message passing systems. It provides the illusion that operations execute sequentially and fault-free, despite the a ...

Assoc Computing Machinery2012

Laws of order

Rachid Guerraoui, Hagit Albo Attiya

Building correct and efficient concurrent algorithms is known to be a difficult problem of fundamental importance. To achieve efficiency, designers try to remove unnecessary and costly synchronization. However, not only is this manual trial-and-error proce ...

2011

Laws of Order: Expensive Synchronization in Concurrent Algorithms Cannot be Eliminated

Rachid Guerraoui, Hagit Albo Attiya

Building correct and efﬁcient concurrent algorithms is known to be a difﬁcult problem of fundamental importance. To achieve ef- ﬁciency, designers try to remove unnecessary and costly synchro- nization. However, not only is this manual trial-and-error proc ...

2011

Automated Model-driven Simulation and Visualization of Field Sensor Data

Karl Aberer, Michael Lehning, Sofiane Sarni, Marc Parlange, Mathias Thierry Pierre Bavay, Silvia Simoni

In the EU project Hydrosys (http://www.hydrosysonline.eu), we have defined and implemented a data processing pipeline that makes simulation process completely automated, fast and transparent to the scientist. Furthermore, our automated simulation tool is f ...

2011

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