Concept

Classic RISC pipeline

Publications associées (72)

Low-Latency Event-Based Visual Odometry

The agility of a robotic system is ultimately limited by the speed of its processing pipeline. The use of a Dynamic Vision Sensors (DVS), a sensor producing asynchronous events as luminance changes are perceived by its pixels, makes it possible to have a s ...

2014

A paradox of eventual linearizability in shared memory

Rachid Guerraoui, Eric Ruppert

This paper compares, for the rst time, the computational power of linearizable objects with that of eventually linearizable ones. We present the following paradox. We show that, unsurprisingly, no set of eventually linearizable objects can (1) implement an ...

ACM Press2014

Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing

David Atienza Alonso, Karim Kanoun, Martino Ruggiero

In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. In this context, stream mining applications are now wi ...

IEEE Press2014

Planck 2013 results. II. Low Frequency Instrument data processing

Xin Chen, Julien Lesgourgues, Fabio Finelli

We describe the data processing pipeline of the Planck Low Frequency Instrument (LFI) data processing centre (DPC) to create and characterize full-sky maps based on the first 15.5 months of operations at 30, 44, and 70 GHz. In particular, we discuss the va ...

Edp Sciences S A2014

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

Among different analog-to-digital converter (ADC) architectures pipelined ADCs are the most suited for medium sampling frequencies (50-300MSPS) and medium resolutions, i.e. 8 to 14 bits. Having the lowest figure-of-merit (FOM) in its bandwidth and resoluti ...

EPFL2012

Making Wide-Issue VLIW Processors Viable on FPGAs

Paolo Ienne, Madhura Purnaprajna

Soft and highly-customized processors are emerging as a common way to efficiently control large amount of computing resources available on FPGAs. Yet, some processor architectures of choice for DSP and media applications, such as wide-issue VLIW processors ...

2012

Reducing OLTP Instruction Misses With Thread Migration

Anastasia Ailamaki, Pinar Tözün

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from h ...

2012

Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL

Marco Mattavelli, Ab Al Hadi Bin Ab Rahman, Anatoly Prihozhy

This paper describes a pipeline synthesis and optimization technique that increases data throughput of FPGA-based system using minimum pipeline resources. The technique is applied on \CAL dataflow language, and designed based on relations, matrices and gra ...

Hindawi Publishing Corporation2011

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