Tong | EPFL Graph Search

thumb|Exemples de tongs, ou claquettes. La tong, tongo, claquette ou nu-pied, aussi appelée gougoune au Québec ou simplement sandale, slache en Belgique francophone mais plus particulièrement à Bruxelles, ou encore savate (savates deux doigts), claquette, sandale dans certaines régions françaises maritimes et d'outre-mer, est une chaussure formée d’une semelle sur laquelle sont fixées deux brides en Y dont la lanière verticale (le « bâton » sur lequel repose le Y), fixée sur la semelle, sépare le gros orteil du reste des orteils du pied. Cette caractéristique distingue depuis quelques dizaines d'années les tongs de ce qui en France métropolitaine et autres régions francophones est appelé des « claquettes », le mot utilisé dans certaines régions, îles ou archipels francophones, comme la Nouvelle-Calédonie, pour désigner les tongs. Avant que la mode des sandales de maître-nageur ne se répande hors des piscines au cours des années 1980, le terme "claquettes" était utilisé en France pour d

System for generating computer processor

A method and apparatus to produce a net list of gates and Flip-Flops for one algorithm in order to find the best compromise between power consumption, speed and silicon surface by using a two step process. First the algorithm is written for a processor that has no restrictions in terms of number and size of register, core, operations set, memory handler and instructions. The program assembly of this processor fits into a two-dimensional table. To increase speed, the tables are configured to place the program operation in as many columns as possible, and to reduce silicon the tables are configured to place operations in a single column with many rows. The second stage consists of converting this virtual processor with its program tables into an HDL file ready for synthesis.

2010

TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Jian Zhang

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. As a promising approach to keep the pace of Moore's Law, functionality-enhanced devices with multiple independent gates have drown many recent interests. In particular, Three-Independent-Gate Silicon Nanowire FETs (TIG SiNWFETs) can realize the functionality of two serial transistors in a single device. Therefore, they open new opportunities to compact designs in both arithmetic and control circuits. In this paper, we propose TSPC flip-flop implementation with asynchronous set and reset using the compactness of TIG SiNWFET. Electrical simulations show that TIG SiNWFET-based TSPC flip-flop improves nearly 20%, 30% and 7% in area, delay and leakage power respectively as compared to its LSTP FinFET counterpart at 22nm.

IEEE2014

FPGA-SPICE: A Simulation-based Power Estimation Framework for FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

Mainstream Field Programmable Gate Array (FPGA) power estimation tools are based on probabilistic activity estimation and analytical power models. The power consumption of the programmable resources of FPGAs is highly sensitive to their configurations. Due to their highly flexible nature, the configurations of FPGAs routing multiplexers or Look Up Tables (LUTs) are really different from a design to another but current analytical power models cannot accurately capture the associated power differences. In this paper, we introduce a simulation-based power estimation framework for FPGAs, called FPGA-SPICE, which supports any FPGA architecture that can be described with an architectural description language. Our power estimation engine automatically generates accurate SPICE netlists according to the FPGA configurations and enables precise power analysis of FPGA architectures. SPICE testbenches can be generated at different level of complexity, denoted as full-chip-level, grid-level and component-level testbenches. Full-chip-level testbenches dump the netlists associated with the complete FPGA fabric. To reduce simulation time, FPGA-SPICE can split the full-chip-level testbenches into grid-level testbenches, each of which consisting of a complete logic block netlist, or component-level testbenches, which consider individual circuit elements, i.e., multiplexers, LUTs, flip-flops, etc., separately. We show that the grid/component-level approach can achieve 14 x speed-up with a moderate 14% accuracy loss, compared to the full-chip level. We also use FPGA-SPICE to study the power characteristics of a commercial FPGA architecture at different technology nodes. Experimental results show that the global routing architecture consumes 50% of the total power, the local routing architecture claims for 40% of the total power, and the remaining 10% comes from the LUTs and flip-flops.

2015

FPGA-SPICE: A Simulation-based Power Estimation Framework for FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

2015