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Concept
Goldmont
Résumé
Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core.
The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzhen, China, April 2016. The Goldmont architecture borrows heavily from the Skylake Core processors, so it offers a more than 30 percent performance boost compared to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.
Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers. Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake.
The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:
An out-of-order execution engine with a 3-wide superscalar pipeline. Specifically:
The decoder can decode 3 instructions per cycle.
The microcode sequencer can send 3 μops per cycle for allocation into the reservation stations.
Retirement supports a peak rate of 3 per cycle.
Enhancement in branch prediction which de-couples the fetch pipeline from the instruction decoder.
Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle (compared to one load or one store per cycle in the Silvermont microarchitecture). The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
Source officielle
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