Electronic system-level design and verification

Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, an EDA-industry-analysis firm, on February 1, 2001. It is defined in ESL Design and Verification as: "the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner." The basic premise is to model the behavior of the entire system using a high-level language such as C, C++, or using graphical "model-based" design tools. Newer languages are emerging that enable the creation of a model at a higher level of abstraction including general purpose system design languages like SysML as well as those that are specific to embedded system design like SMDL and SSDL. Rapid and correct-by-construction implementation of the system can be automated using EDA tools such as high-level synthesis and embedded software tools, although much of it is performed manually today. ESL can also be accomplished through the use of SystemC as an abstract modeling language. ESL is an established approach at many of the world’s leading System-on-a-chip (SoC) design companies, and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with 'no links to implementation', ESL is evolving into a set of complementary methodologies that enable embedded system design, verification, and debugging through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on board, and entire multi-board systems. Design and verification are two distinct disciplines within this methodology. Some practices are to keep the two elements separate, while others advocate for closer integration between design and verification. Whether ESL or other systems, design refers to "the concurrent design of the hardware and software parts of an electronic product.

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Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals

Catherine Dehollain, Naci Pekçokgüler

Medical implant devices have found widespread application in recent years. The Super-Regenerative Receiver has been one preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equivalent models to be used in system level design of a Super-Regenerative Receiver in this paper. The design procedure is also demonstrated with a receiver design example. Designs were carried out in UMC 180 nm process with a center frequency of 416 MHz for MedRadio band. Errors between the simulation results of the proposed model and actual circuits are less than 1.6% for LNA characteristics and 7% for receiver output amplitude. 10 Mbps data rate was achieved with 432 pJ/bit energy consumption over 1.8 V power supply. The study is concluded with the simulation results of the circuits and the equivalent models.

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