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Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these optimizations usually require large dedicated on-chip tables. Although technology ...
Nature is an incredibly complex system resulting from the interactions of many different interdependent species, composed of many individual organisms, which are in turn composed of an extremely large number of cells. In multi-cellular organisms, the paral ...
The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communica ...
Runtime monitoring tools are invaluable for detecting various types of bugs, in both sequential and multi-threaded programs. However, these tools often slow down the monitored program by an order of magnitude or more [4], implying that the tools are ill-su ...
The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a p ...
Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through h ...
The increasing importance,of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the rece ...
Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint ...
We address the quantitative comparison of two basic connection schemes for on-chip communication, connection-oriented and connection-less, regarding their enforcement of a defined Quality-of-Service for the communication. For such comparison, we have built ...
On-chip interconnection networks for future systems on chip (SoC) will have to deal with the increasing sensitivity of global wires to noise sources such as crosstalk or power supply noise. Hence, transient delay and logic faults are likely to reduce the r ...
Institute of Electrical and Electronics Engineers2005
