Publications associées à Additionneur

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub- ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Turbo-Like Structures for Chaos Encoding and Decoding

Martin Hasler, Slobodan Kozic, Francisco Javier Escribano Aparicio

In this paper, we explain how to build a turbo-like structure with binary inputs and chaotic outputs for efficient coding and decoding in additive white Gaussian noise (AWGN). We analyze the convergence of the decoding algorithm, the performance in the err ...

2009

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Optimization of nanoelectronic systems' reliability under massive defect density using Cascaded R-fold modular redundancy

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

The theoretical analysis of R-fold modular redundancy, cascaded R-fold modular redundancy and NAND multiplexing is presented and these fault-tolerant techniques are compared in terms of resistance to massive levels of defect density. Optimal cluster size a ...

2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Alessandro Cevrero, Ajay Kumar Verma, Hadi Parandeh Afshar, Panagiotis Athanasopoulos

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008

A Novel FPGA Logic Block for Improved Arithmetic Performance

Philip Brisk, Hadi Parandeh Afshar

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed loca ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2008

Automatic synthesis of compressor trees: Reevaluating large counters

Paolo Ienne, Ajay Kumar Verma

Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor ro ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

Eric Vittoz, Yusuf Leblebici, Omer Can Akgun

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can ...

2007

Current Sensing Completion Detection for Subthreshold Asynchronous Circuits

Eric Vittoz, Yusuf Leblebici, Omer Can Akgun

In this paper a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The ...

2007

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Additionneur

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Turbo-Like Structures for Chaos Encoding and Decoding

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Optimization of nanoelectronic systems' reliability under massive defect density using Cascaded R-fold modular redundancy

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

A Novel FPGA Logic Block for Improved Arithmetic Performance

Automatic synthesis of compressor trees: Reevaluating large counters

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

Current Sensing Completion Detection for Subthreshold Asynchronous Circuits

On the concentration of the capacity for a code division multiple access system

Graph Chatbot

Chattez avec Graph Search

Automatic synthesis of compressor trees: Reevaluating large counters

Optimization of nanoelectronic systems' reliability under massive defect density using Cascaded R-fold modular redundancy

Turbo-Like Structures for Chaos Encoding and Decoding

A Novel FPGA Logic Block for Improved Arithmetic Performance

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Current Sensing Completion Detection for Subthreshold Asynchronous Circuits

On the concentration of the capacity for a code division multiple access system

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime