Concept
VHDL
Concepts associés (22)
Parallel programming model
In computing, a parallel programming model is an abstraction of parallel computer architecture, with which it is convenient to express algorithms and their composition in programs. The value of a programming model can be judged on its generality: how well a range of different problems can be expressed for a variety of different architectures, and its performance: how efficiently the compiled programs can execute. The implementation of a parallel programming model can take the form of a library invoked from a sequential language, as an extension to an existing language, or as an entirely new language.
Don't-care term
In digital logic, a don't-care term (abbreviated DC, historically also known as redundancies, irrelevancies, optional entries, invalid combinations, vacuous combinations, forbidden combinations, unused states or logical remainders) for a function is an input-sequence (a series of bits) for which the function output does not matter. An input that is known to never occur is a can't-happen term. Both these types of conditions are treated the same way in logic design and may be referred to collectively as don't-care conditions for brevity.