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The ALICE experiment at CERN LHC is intensively using a PROOF cluster for fast analysis and reconstruction. The current system (CAF - CERN Analysis Facility) consists of 120 CPU cores and about 45 TB of local space. PROOF enables interactive parallel proce ...
Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2009
The terminal differentiation of melanocytes is associated with the transcriptional activation of genes responsible for pigment production such as tyrosinase. Pigment cell-specific transcription factors, such as Mitf, as well as specific proximal and distal ...
Runtime monitoring tools are invaluable for detecting various types of bugs, in both sequential and multi-threaded programs. However, these tools often slow down the monitored program by an order of magnitude or more [4], implying that the tools are ill-su ...
There is a rapid rise of multi-cores in recent hardware architectures. To exploit computational power of multi-core architectures, software should shift to be as concurrent as possible; and therefore should have concurrency control mechanisms. There are di ...
Advancements in technology enable integration of multiple devices on a single core, resulting in increased on chip power and temperature densities. Higher temperatures, in turn, present a significant challenge for reliability. In this work we propose a com ...
Are multi-core SoCs being held back by the lack of adequate system design and software development tools? Multi-cores supply the advantages of flexible software-defined architectures, but support for system optimization, integration and verification is lac ...
We propose and demonstrate a reconfigurable tunable encoder for two-dimensional time–wavelength optical code division multiple access (OCDMA). This encoder is capable of creating 2D codes with variable code weight, enabling differentiated service provision ...
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeo ...
This paper proposes an analytical method to assess softerror rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method uses an executable UML model of the SoC for its input. Soft-errors on the design ar ...
The neural simulation tool NEST (http://www.nest-initiative.org) is a simulator for heterogeneous networks of point neurons or neurons with a small number of compartments. It aims at simulations of large neural systems with more than 10^4 neurons and 10^7 ...
