Publications associées à Encapsulation (électronique)

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the applicat ...

2010

RF NEM capacitive switch based on dense horizontal arrays of CNTs

Mihai Adrian Ionescu, László Forró, Arnaud Magrez, Rita Smajda, Ji Cao, Anupama Arun, Donatello Acquaviva

Carbon nanotubes (CNTs) have been considered one of the most promising material to make nanodevices, in particular nanoelectromechanical systems (NEMS), due to their remarkable mechanical (Young's modulus ∼ 1 TPa) and electrical (high conductivity for meta ...

2010

3D-ICE: Fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling

David Atienza Alonso, Arvind Raj Mahankali Sridhar, Martino Ruggiero, Alessandro Vincenzi

Three dimensional stacked integrated circuits (3D ICs) are extremely attractive for overcoming the barriers in interconnect scaling, offering an opportunity to continue the CMOS performance trends for the next decade. However, from a thermal perspective, v ...

ACM and IEEE Press2010

Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries

David Atienza Alonso, Arvind Raj Mahankali Sridhar, Martino Ruggiero, Alessandro Vincenzi

The advent of 3D stacked ICs with accumulating heat fluxes stresses thermal reliability and is responsible for temperature driven performance deterioration of the electronic systems Hot spots with power densities typically rising up to 250 W/cm2 are not ac ...

IEEE Press2010

Process-induced skew variation for scaled 2-D and 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented a ...

ACM Press2010

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Seyed Armin Tajalli, Yusuf Leblebici

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

2010

Inexpensive and fast wafer-scale fabrication of nanohole arrays in thin gold ﬁlms for plasmonics

Jürgen Brugger, Harry Heinzelmann, Mona Julia Katharina Klein, Bernard Wenger, Raphaël Pugin

In this paper, a fast and inexpensive wafer-scale process for the fabrication of arrays of nanoscale holes in thin gold ﬁlms for plasmonics is shown. The process combines nanosphere lithography using spin-coated polystyrene beads with a sputter-etching pro ...

Institute of Physics2010

Foil level packaging of a chemical gas sensor

Nico de Rooij, Danick Briand, Jérôme Courbat

A generic method for the packaging of transducers at the foil level is proposed and was demonstrated on chemical gas sensors made on a plastic foil. The processing was based on the lamination of pre-patterned polymeric structures on the fabricated devices ...

Institute of Physics2010

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Encapsulation (électronique)

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

Spectral analysis and experimental study of lateral capillary dynamics for flip-chip applications

RF NEM capacitive switch based on dense horizontal arrays of CNTs

3D-ICE: Fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling

Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries

Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

Process-induced skew variation for scaled 2-D and 3-D ICs

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Inexpensive and fast wafer-scale fabrication of nanohole arrays in thin gold ﬁlms for plasmonics

Foil level packaging of a chemical gas sensor

Graph Chatbot

Chattez avec Graph Search

Spectral analysis and experimental study of lateral capillary dynamics for flip-chip applications

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries

Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

RF NEM capacitive switch based on dense horizontal arrays of CNTs

3D-ICE: Fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling

Process-induced skew variation for scaled 2-D and 3-D ICs

Inexpensive and fast wafer-scale fabrication of nanohole arrays in thin gold ﬁlms for plasmonics

Foil level packaging of a chemical gas sensor