Concept

Encapsulation (électronique)

Publications associées (212)

Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

Research and development efforts on chip and wafer-scale 3D integration for system miniaturization have been continuing for more than a decade. However, there are still only a handful of 3D integrated products available in the market due to the high cost a ...

EPFL2017

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Mohammad Amin Shokrollahi, Seyed Armin Tajalli, Christoph Walter, Ali Hormati, Anant Pratap Singh, Omid Talebi Amiri, Klaas Lammert Hofstra, Sergio Pesenti

High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a di ...

2016

Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

Mohammad Amin Shokrollahi, Ali Hormati

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herei ...

2016

Chip-scale Optical Resonator Enabled Synthesizer (CORES) Miniature systems for optical frequency synthesis

Tobias Kippenberg, Nicolas Volet, Hairun Guo, Martin Hubert Peter Pfeiffer

An approach for a low-power chip-scale package is described, that provides a laser output with a programmable frequency across 50 nm of bandwidth centered at 1550 nm, and a resolution of one part in 10(14). ...

Ieee2016

Assessment of Confinement-Induced Band-to-Band Tunneling Leakage in the FinEHBTFET

Mihai Adrian Ionescu, Cem Alper, José Luis Padilla de la Torre

In conventional planar EHBTFETs, the interband tunneling phenomena responsible for the drive current takes place vertically in the section of the channel where top and bottom gates overlap. As a result, the horizontal extent of this overlapping between gat ...

Ieee2016

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

Jean-Michel Sallese, Alessandro Mapelli

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic ...

Institute of Physics2016

Deformation behavior of nanoporous polycrystalline silver layers sintered by low temperature bonding: experiment and simulation

Saba Zabihzadeh

Integrated circuit packaging technology has become a prime design consideration for the develop-ment of electronic system concepts. One key issue is the bonding layer between chip and substrate. Currently, high-lead solder materials are being used, which a ...

EPFL2016

An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results

Stanisa Raspopovic, Roberto Puddu

The prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of 2 integrated circuits: a standard CMOS device for neural recording and a HVCM ...

Springer Verlag2016

Magnetoelectric micromachines with wirelessly controlled navigation and functionality

Mahmut Selman Sakar

The use of a single energy source for both manipulating micromachines and triggering their functionalities will result in highly integrated devices and simplify the design of the controlling platform. Here, we demonstrate this concept employing magnetoelec ...

2016

Differential vector storage for dynamic random access memory

Mohammad Amin Shokrollahi, Harm Cronie

A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2.sup.n distinct inputs can be encoded ...

2016

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