Publications associées à Processeur superscalaire

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Ieee2016

Fault Tolerance in the Parareal Method

Jan Sickmann Hesthaven, Allan Svejstrup Nielsen

Parallel-in-time integration is an often advocated approach for extracting parallelism in the solution of PDEs beyond what is possible using spacial domain decomposition tech- niques. Due to the comparatively low parallel efficiency of parallel-in-time int ...

Assoc Computing Machinery2016

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Andreas Peter Burg, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Gabriel Falcao Paiva Fernandes, Madhura Purnaprajna, João Maria Duarte Andrade

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Assoc Computing Machinery2015

Eliminating unscalable communication in transaction processing

Anastasia Ailamaki, Frederick Ryan Johnson, Ippokratis Pandis

Multicore hardware demands software parallelism. Transaction processing workloads typically exhibit high concurrency, and, thus, provide ample opportunities for parallel execution. Unfortunately, because of the characteristics of the application, transacti ...

Springer Verlag2014

Manual Parallelization Versus State-of-the-Art Parallelization Techniques: The SPEC CPU2006 as a Case Study

Aleksandar Vitorovic

Being multiprocessors (both on-chip and/or off-chip), modern computer systems can automatically exploit the benefits of parallel programs, but their resources remain underutilized in executing still-Prevailing sequential applications. An obvious solution i ...

Elsevier Academic Press Inc2014

Dynamic Fine-Grained Scheduling for Energy-Efficient Main-Memory Queries

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Iraklis Psaroudakis, Erietta Liarou

Power and cooling costs are some of the highest costs in data centers today, which make improvement in energy efficiency crucial. Energy efficiency is also a major design point for chips that power whole ranges of computing devices. One important goal in t ...

2014

Privacy-Preserving Optimal Meeting Location Determination on Mobile Devices

Jean-Pierre Hubaux, Imad Aad, Murtuza Jadliwala, Igor Bilogrevic, Vishal Joneja

Equipped with state-of-the-art smartphones and mobile devices, today's highly interconnected urban population is increasingly dependent on these gadgets to organize and plan their daily lives. These applications often rely on current (or preferred) locatio ...

Ieee-Inst Electrical Electronics Engineers Inc2014

Two-Phase Flow Control of Electronics Cooling With Pseudo-CPUs in Parallel Flow Circuits: Dynamic Modeling and Experimental Evaluation

John Richard Thome, Jackson Braz Marcinichen, Nicolas Lamaison

On-chip two-phase cooling of parallel pseudo-CPUs integrated into a liquid pumped cooling cycle is modeled and experimentally verified versus a prototype test loop. The system's dynamic operation is studied since the heat dissipated by microprocessors is c ...

American Society of Mechanical Engineers2013

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Processeur superscalaire

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Fault Tolerance in the Parareal Method

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Transactions Chasing Scalability and Instruction Locality on Multicores

Eliminating unscalable communication in transaction processing

Manual Parallelization Versus State-of-the-Art Parallelization Techniques: The SPEC CPU2006 as a Case Study

A Primer on Hardware Prefetching

Dynamic Fine-Grained Scheduling for Energy-Efficient Main-Memory Queries

Privacy-Preserving Optimal Meeting Location Determination on Mobile Devices

Two-Phase Flow Control of Electronics Cooling With Pseudo-CPUs in Parallel Flow Circuits: Dynamic Modeling and Experimental Evaluation

Graph Chatbot

Chattez avec Graph Search

Transactions Chasing Scalability and Instruction Locality on Multicores

Privacy-Preserving Optimal Meeting Location Determination on Mobile Devices

Dynamic Fine-Grained Scheduling for Energy-Efficient Main-Memory Queries

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Eliminating unscalable communication in transaction processing

A Primer on Hardware Prefetching

Manual Parallelization Versus State-of-the-Art Parallelization Techniques: The SPEC CPU2006 as a Case Study

Two-Phase Flow Control of Electronics Cooling With Pseudo-CPUs in Parallel Flow Circuits: Dynamic Modeling and Experimental Evaluation

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Fault Tolerance in the Parareal Method