Publications associées à Sauvegarde (informatique)

Beating the I/O Bottleneck: A Case for Log-Structured Virtual Disks

With the increasing dominance of SSDs for local storage, today's network mounted virtual disks can no longer offer competitive performance. We propose a Log-Structured Virtual Disk (LSVD) that couples log-structured approaches at both the cache and storage ...

ASSOC COMPUTING MACHINERY2022

Fine-Grain Checkpointing with In-Cache-Line Logging

James Richard Larus, David Teksen Aksun, Nachshon Cohen

Non-Volatile Memory offers the possibility of implementing high-performance, durable data structures. However, achieving performance comparable to well-designed data structures in non-persistent (transient) memory is difficult, primarily because of the cos ...

ACM2019

Closing the Performance Gap Between Volatile and Persistent Key-Value Stores Using Cross-Referencing Logs

Matej Pavlovic

Key-Value (K-V) stores are an integral building block in modern datacenter applications. With byteaddressable persistent memory (PM) technologies, such as Intel/Micron's 3D XPoint, on the horizon, there has been an influx of new high performance K-V stores ...

USENIX ASSOC2018

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Seyed Armin Tajalli, Paul Victor Georges Muller, Yusuf Leblebici

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

Seyed Armin Tajalli, Paul Victor Georges Muller, Yusuf Leblebici

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are d ...

IEEE2006

Reliability Support for On-chip Memories Using Networks-on-Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

2006

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...

EPFL2006

Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

Paul Victor Georges Muller, Yusuf Leblebici

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data ...

2005