Publications associées à Accès direct à la mémoire

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported f ...

ELSEVIER SCI LTD2020

Access pattern based optimization of memory access

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include identifying an access pattern associated with a database operation. The access pattern may include data required to perform the database operation. One or mor ...

2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow cell arrays (FCAs) provide efficient on-chip liquid cooling and electrochemical power generation capabilities in three-dimensional multi-processor systems-on-chip (3DMPSoCs). When connected to power delivery networks (PDNs) of chips, the current flowi ...

2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Mirjana Stojilovic, Philip Brisk, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Data-Driven Distributed Combined Primary and Secondary Control in Microgrids

Alireza Karimi, Christoph Manuel Kammer, Seyed Sohail Madani

This paper presents a comprehensive data-driven distributed combined primary/secondary controller design method for microgrids. This method provides transient and steady-state performance including power-sharing and voltage and frequency restoration while ...

2020

Pythia: Remote Oracles for the Masses

Mathias Josef Payer, Yuqing Zhang

Remote Direct Memory Access (RDMA) is a technology that allows direct access from the network to a machine's main memory without involving its CPU. RDMA offers low-latency, high-bandwidth performance and low CPU utilization. While RDMA provides massive per ...

USENIX ASSOC2019

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

Paolo Ienne, Mikhail Asiatici, Gabor Andras Csordas

For efficient acceleration on FPGA, it is essential for external memory to match the throughput of the processing pipelines. However, the usable DRAM bandwidth decreases significantly if the access pattern causes frequent row conflicts. Memory controllers ...

IEEE COMPUTER SOC2019

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Accès direct à la mémoire

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Access pattern based optimization of memory access

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Data-Driven Distributed Combined Primary and Secondary Control in Microgrids

Pythia: Remote Oracles for the Masses

Improving Main-memory Database System Performance through Cooperative Multitasking

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Graph Chatbot

Chattez avec Graph Search

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Access pattern based optimization of memory access

Improving Main-memory Database System Performance through Cooperative Multitasking

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Data-Driven Distributed Combined Primary and Secondary Control in Microgrids

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Pythia: Remote Oracles for the Masses

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA