Concept
Gate array
Personnes associées (35)
Edoardo Charbon
voir version Anglaise
Mihai Adrian Ionescu
D'origine et de nationalités roumaine et suisse, Mihai-Adrian Ionescu est né en 1965. Après le doctorat en Physique des Composants à Semiconducteurs de lInstitut National Polytechnique de Grenoble, M. Ionescu a travaillé comme chercheur post-doctoral au LETI-CEA Grenoble, sur la caractérisation des diélectriques low-k pour les technologies submicroniques CMOS. Après une courte période au sein du CNRS, comme chargé de recherche 1ere Classe il a effectué un séjour post-doctoral au Center for Integrated Systems, Stanford University, USA. Actuellement il est Professeur Nanoélectronique à lEcole Polytechnique Fédérale de Lausanne.
Paolo Ienne
Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
Mirjana Stojilovic
Mirjana Stojilović received the Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. From 2010 to 2013, she was collaborating with the Processor Architecture Laboratory at EPFL, visiting periodically as a Guest Researcher. From 2013 to 2016, she was working at the University of Applied Sciences Western Switzerland as a senior researcher, and at EPFL as a lecturer. She joined Parallel Systems Architecture Lab at EPFL in October 2016. Mirjana's main research interests include electronic design automation, reconfigurable computing, electromagnetic-compatibility and signal-integrity issues, and hardware security. Mirjana Stojilović serves on the program committee of the FPGA, FPL, and FCCM conferences and as a reviewer for IEEE TCAD, TVLSI, TC, TEMC, IEEE Access and ACM TRETS. She received the Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016), Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016), and the Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012). In 2015, the EPFL School of Computer and Communication Sciences (IC) presented her with the Teaching Award.
David Atienza Alonso
David Atienza Alonso is an associate professor of EE and director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in computer science and engineering from UCM, Spain, and IMEC, Belgium, in 2001 and 2005, respectively. His research interests include system-level design methodologies for multi-processor system-on-chip (MPSoC) servers and edge AI architectures. Dr. Atienza has co-authored more than 350 papers, one book, and 12 patents in these previous areas. He has also received several recognitions and award, among them, the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, Design Automation Conference (DAC) Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He has also earned two best paper awards at the VLSI-SoC 2009 and CST-HPCS 2012 conference, and five best paper award nominations at the DAC 2013, DATE 2013, WEHA-HPCS 2010, ICCAD 2006, and DAC 2004 conferences. He serves or has served as associate editor of IEEE Trans. on Computers (TC), IEEE Design & Test of Computers (D&T), IEEE Trans. on CAD (T-CAD), IEEE Transactions on Sustainable Computing (T-SUSC), and Elsevier Integration. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. He served as President of IEEE CEDA in the period 2018-2019 and was GOLD member of the Board of Governors of IEEE CASS from 2010 to 2012. He is a Distinguished Member of ACM and an IEEE Fellow.
Mario Paolone
Mario Paolone received the M.Sc. (with honors) and the Ph.D. degree in electrical engineering from the University of Bologna, Italy, in 1998 and 2002, respectively. In 2005, he was appointed assistant professor in power systems at the University of Bologna where he was with the Power Systems laboratory until 2011. In 2010, he received the Associate Professor eligibility from the Politecnico di Milano, Italy. Since 2011 he joined the Swiss Federal Institute of Technology, Lausanne, Switzerland, where he is now Full Professor, Chair of the Distributed Electrical Systems laboratory and Head of the Swiss Competence Center for Energy Research (SCCER) FURIES (Future Swiss Electrical infrastructure). He was co-chairperson of the technical programme committees of the 9th edition of the International Conference of Power Systems Transients (IPST 2009) and of the 2016 Power Systems Computation Conference (PSCC 2016). He was chair of the technical programme committee of the 2018 Power Systems Computation Conference (PSCC 2018). In 2013, he was the recipient of the IEEE EMC Society Technical Achievement Award. He was co-author of several papers that received the following awards: best IEEE Transactions on EMC paper award for the year 2017, in 2014 best paper award at the 13th International Conference on Probabilistic Methods Applied to Power Systems, Durham, UK, in 2013 Basil Papadias best paper award at the 2013 IEEE PowerTech, Grenoble, France, in 2008 best paper award at the International Universities Power Engineering Conference (UPEC). He was the founder Editor-in-Chief of the Elsevier journal Sustainable Energy, Grids and Networks and was Associate Editor of the IEEE Transactions on Industrial Informatics. His research interests are in power systems with particular reference to real-time monitoring and operation, power system protections, power systems dynamics and power system transients. Mario Paolone is author or coauthor of over 300 scientific papers published in reviewed journals and international conferences.
Pierre-André Farine
Pierre-André Farine received the Doctoral and Engineering Degrees in Microtechnology from University of Neuchâtel, Switzerland, respectively in 1984 and 1978, and the Engineering in Microtechnology from ETS Le Locle in 1974.
He was working 17 years for the Swiss watch industries (Swatch Group), including developments for high-tech products, such as pager watches, watches including integrated sensors such as pressure, compass, altimeter and temperature sensors for Tissot. He was also involved in prototypes developments for watches including GPS and cellular GSM phones.
Since 8 years, he is Professor in Electronics and Signal Processing at the Institute of Microtechnology IMT, University of Neuchâtel, Switzerland. Full professor at EPFL since January 1st, 2009, he works in the field of low-power integrated products for portable devices, including microelectronics for wireless telecommunications, UWB and GNSS systems. He is Head of the Electronics and Signal Processing Laboratory ESPLAB of the EPFL IMT-NE. His laboratory works also for video and audio compression algorithms and their implementation in low power integrated circuits.
Claudio Bruschini
Claudio Bruschini holds an MSc in high energy physics from the University of Genova and a PhD in Applied Sciences from the Vrije Universiteit Brussel (VUB). He started his career with INFN (Italy, 1993), in the WA92 CERN collaboration (particle physics), and then moved to CERN as a Fellow in the European GP-MIMD2 project, attached to the NA48 collaboration (particle physics, parallel programming, 1994-1995). He then started his close collaboration with EPFL, first in the DeTeC (Demining Technology Center) project (sensors for landmine detection/humanitarian demining, 1996-1997). After DeTeC's end, he started the first of a series of fruitful collaborations with the Vrije Universiteit Brussel (VUB) on humanitarian demining related R&D (1998). This was followed by the EUDEM survey project (The European Union in Humanitarian Demining, 1998), the EUDEM2 three year EC sponsored support measure (www.eudem.info, 2001-2004), and the DELVE support action (www.delve.vub.ac.be, 2007). In parallel he started working within the EPFL's AQUA group (Advanced Quantum Architectures, Edoardo Charbon), on topics as diverse as ultrasonic sensors for in-air application, optical 3D and high speed 2D sensing, sensor networks, or tracking/motion capture systems, in particular for the preparation of research projects. This culminated in the European MEGAFRAME (www.megaframe.eu, FP6, 2006-2010, SPAD arrays and related in-pixel time stamping electronics in deep submicron CMOS technology) and SPADnet (www.spadnet.eu, FP7, 2010-2014, networked SPAD arrays for Positron Emission Tomography) projects, coordinated by EPFL-AQUA. As from 2009 he also worked with Dario Floreano on the management of the CURVACE Curved Artificial Compound Eyes FP7 project (www.curvace.org), coordinated by EPFL-LIS. He was also active with CHUV (Lausanne University Hospital) within EndoTOFPET-US (endoscopic PET) as well as on a CTI project devoted to the development of a new hand-held standalone tool for tracer-guided medical procedures. In 2014 he had also the pleasure of joining the EPFL ICLAB of Christian Enz during its ramp-up phase, collaborating on device related topics (SNF GigaRadMOST) and biomedical R&D (NanoTera WiseSkin). Claudio is now fully with EPFL’s Advanced Quantum Architecture (AQUA). He has also been active as independent scientific consultant, under the label CBR Scientific Consulting, on the preparation of (European) R&D project proposals and the execution of individual studies, and worked in 2006 for a local start-up as operations manager and R&D advisor.... but this is another story. An unauthorized early biography is available at http://lami.epfl.ch/team/claudiob/...