Architecture ARM

Résumé

Les architectures ARM sont des architectures externes de type RISC 32 bits (ARMv1 à ARMv7) et 64 bits (ARMv8) développées par ARM Ltd depuis 1983 et introduites à partir de 1990 par Acorn Computers. L'architecture ARM est le fruit du travail de Sophie Wilson. Dotés d'une architecture relativement plus simple que d'autres familles de processeurs et faibles consommateurs d'électricité, les processeurs ARM sont aujourd'hui dominants dans le domaine de l'informatique embarquée, en particulier la téléphonie mobile et les tablettes. Ces processeurs sont fabriqués sous licence par un grand nombre de constructeurs. SoC ARM vignette|300px|redresse|Diagramme d'un SoC ARM. Aujourd'hui, ARM est surtout connu pour ses systèmes sur une puce (SoC), intégrant sur une seule puce : microprocesseur, processeur graphique (GPU), DSP, FPU, SIMD, et contrôleur de périphériques. Ceux-ci sont présents dans la majorité des smartphones et tablettes. ARM propose des architectures qui sont vendues s

Source officielle

https://fr.wikipedia.org/wiki/Architecture_ARM

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EPFL1998

Chargement

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, the automotive applications are also affected by the passion around the electronic devices that are programmable. This thesis work will focus on embedded applications based on programmable processing unit. Indeed, nowadays, for time to market reasons, re-use and flexibility are important parameters. Consequently, embedded processors seem to be the solution because the behavior of the circuit can be modified by software what does not cost a lot compared to Application Specific Integrated Circuits (ASICs) or Digital Signal Processors (DSPs) where hardware modifications are necessary. This choice is judicious compared to multi-pipeline processors like superscalar or Very Long Instruction Word (VLIW) architectures or even in comparison to a Field Programmable Gate Array (FPGA) which require more silicon area, consume more energy and are not as robust as simple scalar processors. Nevertheless, commercial scalar processors, dedicated to embedded systems, have poor frequencies which has a negative effect on their performance. This phenomenon is even more visible with deep-submicron technologies where the primary memories and wire delays do not scale as fast as the logic. Furthermore, the memory speed decreases when their capacity of storage increases and depends on both their organization (associativity, word size, etc.) and the IPs of the foundry. Likewise, synthesizable IP memories have a greater access time than their hard macrocell counterparts. This thesis work proposes a new synthesizable architecture for scalar embedded processors dedicated to alleviate the drawbacks previously mentioned and called Memory Wall : so, its goal is to push back the limits of frequency without introducing wasted cycles used to solve data and control dependencies, independently of the foundry. The architecture that came out, called Deep Submicron RISC (DSR), is made up of a single pipeline with eight stages that executes the instructions in order. In addition to tackle the memory access time and to alleviate the delays of wires, it is appropriate to minimize the power consumption. The proposed architecture is compared to two MIPS architectures, the MIPS R3000 and the MIPS32 24k in order to be able to analyze the performance of the architectures themselves, independently of both Instruction Set (ISA) MIPS 1 and compiler. The R3000 is a processor born in the 90's and the 24k came out in 2004. Obviously, the study reveals that the five-stage processor remains efficient – especially in comparison to the MIPS24k – when the critical path passes by the core and not by the primary memories. Even if the MIPS24k tackles in part the Memory Wall, DSR is much more efficient and reach a gain of efficiency – defined as performance/surface – of 72% thanks to its High-density version (DSR-HD) compared to a five-stage processor. DSR is even more efficient than the two MIPS processors when the transistor channel length decreases, the wire delays are important or the memories are large and their organization complex.

EPFL2007

Chargement

Cellular metallic materials have emerged as a new promising class of materials due to their lightweight porous structures and advanced multi-functional properties. Originally limited to random metallic foams, modern lithography techniques have enabled the design of hierarchical cellular structures with tailored mechanical properties. In addition, the mechanical properties of micro-cellular metals can be further improved by taking advantage of the properties of metals, which are size-sensitive at this length scale. It is therefore expected that the combination of architectured cellular designs with size effects in metals would result in materials with unprecedented mechanical properties. The present thesis aims at investigating and understanding the influence of size effects on the mechanical properties of three-dimensional micro-architectured metal structures synthesized using advanced lithography techniques and electrochemical deposition of metals. Electrodeposited copper films with engineered microstructures and nickel-based hierarchical micro-cellular structures were manufactured and tested under uniaxial loading conditions. The results of the tests were used to evaluate the contribution of the size effects and/or architecture to the change in mechanical properties and deformation behavior. The influence of the intrinsic size effect was first demonstrated in electrodeposited pure copper films. Using nanoscale twins to engineer the grain boundaries, it was possible to produce copper films with high strength and significantly tune the mechanical properties by adjusting the twin orientation. The combination of size effects was then investigated for two types of micro-architecture. The first type of metal micro-architecture was obtained by plating nanocrystalline Ni inside a self-assembled colloidal crystal of microspheres in order to produce a regular inverse opal. The second type was fabricated by metallizing a 3D polymer template produced by 3D laser lithography with an amorphous NiB coating. Results show that there is a complex interaction between the characteristic external dimension and cellular structure. For regular Ni inverse opal, there is a complex interaction between the ligament size and the grain size which defines the overall strength of cellular metals. In the case of hybrid NiB/polymer structures, the brittle-to-ductile transition in the amorphous NiB coating and the architecture effect are coupled. By varying the NiB thickness and the architecture geometry, it is possible to control the deformation mechanism from global buckling to brittle failure and to tune the energy absorption characteristics of the micro-architectures. Through these case studies, it was demonstrated that the combination of grain boundary engineering, sub-micron geometrical features and overall architecture can yield 3D metallic micro-architectures, which are both light and strong and have tailored mechanical properties. The mechanical properties of some of these materials exceed the properties of either of the parent materials. Therefore, the constitutive mechanical laws for porous metals should be modified to account for these three effects all together. The results confirmed the potential of our experimental approach and provide a practical way to extend the material property-space.

EPFL2018

Chargement

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

EPFL2007

EPFL2018