Concept

Verilog

Publications associées (58)

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Formal Analysis of SystemC Designs in Process Algebra

Hossein Hojjat

SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC designs by providing a mapping to the process algebra mCRL2. Our ...

2011

VHDL-AMS Model of an Electrochemical Cell to Design VLSI Bio-Chips

Giovanni De Micheli, Sandro Carrara, Yusuf Leblebici, Alain Vachoux, Marialaura Beltrandi

This paper presents a new VHDL-AMS behavioral model of an electrochemical cell suitable for the design of VLSI bio-chips. Existing models are mainly equivalent circuit macromodels using electrical primitives, which hardly fit the actual behavior of biosens ...

2011

Reliability of Nanoscale Circuits and Systems

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures Milos Stanisavljevic Alexandre Schmid Yusuf Leblebici Future integrated circuits are expected to be made of emerging nanodevices and their associated interconnects, but ...

Springer2011

Support pour l'analyse dimensionnelle en SystemC-AMS

Yusuf Leblebici, Alain Vachoux

La modélisation de systèmes hétérogènes conservatifs multi-domaines (électrique, mécanique, fluidique, etc.) requiert un moyen de vérifier que les quantités manipulées par les modèles aient des unités cohérentes. Nous présentons ici les fondations pour le ...

École Polytechnique Fédérale de Lausanne (EPFL)2009

Supporting Dimensional Analysis in SystemC-AMS

Alain Vachoux

This paper will introduce new modeling capabilities for SystemC-AMS to describe energy conserving multi-domain systems in a formal and consistent way at a high level of abstraction. To this end, all variables and parameters of the system model need to be a ...

IEEE2009

Using 3D Integration Technology To Realize Multi-Context Fpgas

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar, Maurizio Skerlj

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2009

Using 3D integration technology to realize multi-context FPGAs

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar, Panagiotis Athanasopoulos, Maurizio Skerlj

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Supporting Dimensional Analysis in SystemC-AMS

Alain Vachoux

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Emotion on FPGA: Model Driven Approach

Arash Arami

Implementation of intelligent and bio-inspired algorithms in industrial and real applications is arduous, time consuming and costly; in addition, many aspects of system from high level behavior of algorithm to energy consumption of targeted system must be ...

Elsevier2009

Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits

The paper presents several improvements to our synthesis platform Xsynth that was developed targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having implemented an efficient exhaustive k-feasible cone generator it was targ ...

2009