Horloge | EPFL Graph Search

300px|vignette|Le Gros-Horloge de Rouen, horloge astronomique (Époque Renaissance). Une horloge est un instrument de mesure du temps qui généralement indique l'heure en continu. Le mot vient du latin , « qui dit l’heure », lui-même dérivé du grec ὡρολόγιον (formé à partir de oρα, « l'heure », et de λέγειν, « dire », λόγιον, « le dire »). Depuis l'Antiquité, le terme latin « horologium » désigne tout instrument susceptible d'indiquer l'heure, ce qui a mené bien souvent à des difficultés d'interprétation des textes anciens. Ainsi, un cadran solaire, une horloge hydraulique, un astrolabe, un nocturlabe, une horloge mécanique étaient-ils qualifiés d'« horologia ». Après une analyse des informations inhérentes au temps, seront présentés ici, succinctement, les différents types d'horloges, au sens étymologique du terme, en suivant approximativement leur chronologie. Le temps et les horloges Dans une représentation graphique de l'écoulement du temps physique, on peut distingue

L2 output feedback control of delayed linear parameter varying systems with piecewise constant parameters: A clock-dependent L-K approach

Saeed Ahmed, Muhammad Zakwan

This article proposes a new clock-dependent gain-scheduled dynamic output feedback controller for delayed linear parameter varying systems with piecewise constant parameters. The proposed controller guarantees Script capital L2-performance. By employing a clock-dependent Lyapunov-Krasovskii functional, a sufficient condition for the existence of the controller is provided in terms of clock- and parameter-dependent linear matrix inequalities. A case study on output feedback control of delayed switched systems is also provided. To illustrate the efficacy of the result, it is applied to a practical VTOL helicopter model.

2020

Simulation of Instability in Time-Sensitive Networks with Regulators and Imperfect Clocks

Guillermo Aguirre Rodrigo

Regulators are used in time-sensitive networks in order to reshape traffic reducing the burstiness generated by the aggregation systems within the network. Regulators, in terms of the IEEE TSN group are defined as Asynchronous Traffic Shaping or what in the literature is known as interleaved regulators. These regulators are placed before a multiplexing stage, shaping the outgoing traffic and cancelling the increased burstiness, allowing calculations of the worst-case delay to be performed. One of the main properties studied for regulators implies that they do not increase the worst-case delay in the network. So far, all the studies were performed assuming ideal clocks within the network. However, a recently published paper underlines the importance of taking into account non-ideal clocks while studying interleaved regulators properties, providing a theoretical proof that under certain circumstances, interleaved regulators can lead to system instability due to the unbounded delay through them. This thesis intends to continue with this study, providing a simulation proof that shows instability when interleaved regulators are simulated assuming non-ideal clocks. This is carried out in the network simulator ns-3. Along with the different developed modules, two are highlighted: local time and ATS modules. The former introduces the notion of local times in ns-3, whereas the latter implements regulators functionality in ns-3, following the implementation proposed by the IEEE TSN.

2020

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in particular from their instruction sets point of view. As a result, these architectures have a more efficient instruction decoding and smaller computing units which in turn provides the ability to have more of these units for the same price, a reduced clock per instruction ratio — a single cycle per instruction ideally — and increased clock frequencies. As time goes by, RISC architectures have shown outstanding performances, on one hand with the spectacular improvements of semiconductor technologies, and on the other hand with the use of large cache memories and with the development of new ways of execution such as speculative execution. Later developments have greatly altered the original spirit of the simplicity of the RISC concept. Current high performance processors are extremely complex and difficult to design. Moreover, semiconductor technologies begin to show serious problems ignored or neglected for a long time. In this thesis, we would like to introduce a new architecture. Two complementary aspects have been taken in consideration : the design of the processor's units (arithmetic operators, control logic, and so on) and the architectural model, the way the processing units are used. The first aspect has been addressed with an unusual and original approach which involves the use of the serial arithmetic principles. Serial arithmetic tends to reduce the hardware cost, enables higher clock rates, and shows interesting properties which will be developped later on. The research of an architectural model is driven by the same wish of simplicity, recurrent in this field, and will inevitably shift the complexity from the processor to the compiler. This simplification relies on two things : first, the way we think of the problem is inspired by the EPIC philosophy (Explicitly Parallel Instruction Computer), the latest offspring of the VLIW model which advocates the delegation of decisions from the hardware to the software. In one sentence, "the compiler decides, the hardware executes". Second, the way we act has been given by the TTA model (Transport Triggered Architecture), the last offspring of the MOVE model which not only removes from the processor the responsability to decide which processing unit to be used for each instruction (it's already the case in a VLIW processor), but also releases the processor from scheduling the data flows. In doing so, the processor is confined to provide a set of computing units, storage units and means of communication, and the compiler decides how to move the data. In this way, a part of the control logic is removed, communication resources may be fine-tuned and the compiler's code-optimization can be enhanced. With the combination of those elements, we wish to get an architecture which exhibits a better computing power/consumption ratio, which is more flexible, easier to developp and to evolve.

EPFL2004

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

EPFL2004