Publications associées à Nehalem

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Babak Falsafi, Mathias Josef Payer, Atri Bhattacharyya

Spectre, Meltdown, and related attacks have demonstrated that kernels, hypervisors, trusted execution environments, and browsers are prone to information disclosure through micro-architectural weaknesses. However, it remains unclear as to what extent other ...

ACM2019

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

On the Performance of Delegation over Cache-Coherent Shared Memory

André Schiper, Thomas Ropars, Darko Petrovic

Delegation is a thread synchronization technique where access to shared data is performed through a dedicated server thread. When a client thread requires shared data access, it makes a request to a server and waits for a response. This paper studies deleg ...

2015

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Sotiria Fytraki, Evangelos Vlachos

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu ...

2014

Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman, Mohammad Alisafaee, Yusuf Onur Koçberber, Stavros Volos, Ilknur Cansu Kaynak, Adrian Daniel Popescu, Al Mutaz Adileh, Dorde Jevdic

Emerging scale-out workloads require extensive amounts of computational resources. However, data centers using modern server hardware face physical constraints in space and power, limiting further expansion and calling for improvements in the computational ...

Association for Computing Machinery2012

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Nehalem

Rebooting Virtual Memory with Midgard

Nonlinear Inverse Problems in Quantitative Phase Imaging

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

On the Performance of Delegation over Cache-Coherent Shared Memory

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors

Graph Chatbot

Chattez avec Graph Search

Rebooting Virtual Memory with Midgard

Nonlinear Inverse Problems in Quantitative Phase Imaging

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

On the Performance of Delegation over Cache-Coherent Shared Memory

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors