Concept

Compilateur de compilateur

Publications associées (96)

StagedSAC: a case study in performance-oriented DSL development

Martin Odersky, Tiark Rompf, Vlad Ureche, Hassan Chafi

Domain-specific languages (DSLs) can bridge the gap between high-level programming and efficient execution. However, implementing compiler tool-chains for performance oriented DSLs requires significant effort. Recent research has produced methodologies and ...

ACM2011

Lightweight Modular Staging: A Pragmatic Approach to Runtime Code Generation and Compiled DSLs

Martin Odersky, Tiark Rompf

Software engineering demands generality and abstraction, performance demands specialization and concretization. Generative programming can provide both, but the effort required to develop high-quality program generators likely offsets their benefits, even ...

2010

Lightweight Modular Staging: A Pragmatic Approach to Runtime Code Generation and Compiled DSLs

Martin Odersky, Tiark Rompf

2010

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Philip Brisk, Ajay Kumar Verma, Hadi Parandeh Afshar

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Optimizing Transactions for Captured Memory

Aleksandar Dragojevic

In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is memory allocated inside a transaction, which cannot escape (i.e., is capture ...

ACM2009

Jakstab: A Static Analysis Platform for Binaries

Johannes Kinder

For processing compiled code, model checkers require accurate model extraction from binaries. We present our fully configurable binary analysis platform Jakstab, which resolves indirect branches by multiple rounds of disassembly interleaved with dataflow a ...

Springer2008

Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

David Atienza Alonso, José Luis Ayala Rodrigo, Pablo Garcia del Valle

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be ...

IEEE Computer Society2008

An Intorduction to the Interface Between C and R

This manual will be useful for people looking to extend R with the C compiled code. The motivation for using the C interface with R may be bidirectional. For statisticians programming mainly in R, an interface to C provides fast execution of code and bette ...

2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed varia ...

2007

Reengineering Standard Java Runtime Systems through Dynamic Bytecode Instrumentation

Philippe Moret

Java bytecode instrumentation is a widely used technique, especially for profiling purposes. In order to ensure the instrumentation of all classes in the system, including dynamically generated or downloaded code, instrumentation has to be performed at run ...

2007

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