Concept
Memory barrier
Publications associées (32)
MALTA3: Concepts for a new radiation tolerant sensor in the TowerJazz 180 nm technology
The upgrade of the MALTA DMAPS designed in Tower 180 nm CMOS Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x10(15) 1 MeVn(eq)/cm(2). ...
ELSEVIER2022How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System
Paolo Ienne, Mikhail Asiatici, Damian Maiorano
String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...
SPRINGER2021A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer
Mirjana Stojilovic, Philip Brisk, Frédéric Gessler
RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...
IEEE2020FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort
Paolo Ienne, Mikhail Asiatici, Damian Maiorano
String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...
IEEE COMPUTER SOC2020Lock-Unlock: Is That All? A Pragmatic Analysis of Locking in Software Systems
Rachid Guerraoui, Vasileios Trigonakis
A plethora of optimized mutex lock algorithms have been designed over the past 25 years to mitigate performance bottlenecks related to critical sections and locks. Unfortunately, there is currently no broad study of the behavior of these optimized lock alg ...
2019Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores
Boris Robert Grot, Siddharth Gupta
In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...
IEEE2019Computational characteristics and hardware implications of brain tissue simulations
Understanding the link between the brain's anatomy and its function through computer
simulations of neural tissue models is a widely used approach in computational neuroscience.
This technique enables rapid prototyping and testing of hypotheses, allowing r ...
EPFL2019Scalable Synchronization in Shared-Memory Systems: Extrapolating, Adapting, Tuning
As hardware evolves, so do the needs of applications. To increase the performance of an application,
there exist two well-known approaches. These are scaling up an application, using a larger multi-core
platform, or scaling out, by distributing work to mul ...
EPFL2018Efficient Logging in Non-Volatile Memory by Exploiting Coherency Protocols
James Richard Larus, Nachshon Cohen
Non-volatile memory (NVM) technologies such as PCM, ReRAM and STT-RAM allow processors to directly write values to persistent storage at speeds that are significantly faster than previous durable media such as hard drives or SSDs. Many applications of NVM ...
ACM2017Resolve: Enabling Accurate Parallel Monitoring under Relaxed Memory Models
Babak Falsafi, Sotiria Fytraki, Evangelos Vlachos
Hardware-assisted instruction-grain monitoring frameworks provide high-coverage, low overhead debugging support for parallel programs. Unfortunately, existing frameworks are ill-suited for the relaxed memory models employed by nearly all modern processor a ...
2014