Concept

Architecture de processeur

Publications associées (233)

Platform-independent profiling in a virtual execution environment

Virtual execution environments, such as the Java virtual machine, promote platform-independent software development. However, when it comes to analyzing algorithm complexity and performance bottlenecks, available tools focus on platform-specific metrics, s ...

2008

Application of the Lightsolve methodology for the pre-design of the new Belgian VELUX headquarters

Marilyne Andersen, Magali Bodart

Through the example of the VELUXBelgium building, this paper presents a real case application of a new methodology that is being developed to favor an interactive and intuitive approach of daylighting in buildings in the schematic design phase. The Lightso ...

2008

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Giovanni De Micheli, David Atienza Alonso

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems on Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...

2008

A Rate-based Prefiltering Approach to BLAST Acceleration

Dionysios Pnevmatikatos, Sotiria Fytraki

DNA sequence comparison and database search have evolved in the last years as a field of strong competition between several reconfigurable hardware computing groups. In this paper we present a BLAST preprocessor that efficiently marks the parts of the data ...

2008

Design and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Density

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic, Maria Gabrani

This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random fail ...

ACM2007

An IEEE 802.11a baseband receiver implementation on an application specific processor

Andreas Peter Burg

This paper describes the implementation of the complete baseband processing of an IEEE 802.11a receiver on a design-framework for application specific processors. The underlying generic architecture is described, the computational kernels required for an I ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007

Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management ...

2007

Current Sensing Completion Detection for Subthreshold Asynchronous Circuits

Eric Vittoz, Yusuf Leblebici, Omer Can Akgun

In this paper a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The ...

2007

Low Overhead DFT Using CDFG by Modifying Controller

Pejman Lotfi Kamran

A novel design-for-test (DFT) method that requires minor modifications to the controller in the register-transfer level (RTL) description of a circuit is presented. The control/data flow graph representation of an RTL circuit is used for analysing the test ...

2007

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

Eric Vittoz, Yusuf Leblebici, Omer Can Akgun

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can ...

2007

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