Publications associées à Green thread

Rachid Guerraoui, Vasileios Trigonakis, Karolos Antoniadis

In a non-uniform memory access machine, the placement of software threads to hardware cores can have a significant effect on the performance of concurrent applications. Detecting the best possible placement for each application is a necessity for thread sc ...

IEEE COMPUTER SOC2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Mirjana Stojilovic, Philip Brisk, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Biomolecular Simulation: a Perspective from High Performance Computing

Ursula Röthlisberger, Viacheslav Bolnykh, Paolo Carloni

High-Performance Computing is impacting on all biomedical sciences, including molecular biophysics. Here, we describe general parallel computing strategies (multi-threading and distributed computing) used in all the natural sciences, including molecular bi ...

WILEY-V C H VERLAG GMBH2020

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Boris Robert Grot, Siddharth Gupta

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

IEEE2019

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Mirjana Stojilovic, Philip Brisk

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

FPGAs (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However FPGAs suffer from 3 major drawbac ...

IEEE2018

Interleaving with Coroutines: A Practical Approach for Robust Index Joins

Anastasia Ailamaki, Georgios Psaropoulos

Index join performance is determined by the efficiency of the lookup operation on the involved index. Although database indexes are highly optimized to leverage processor caches, main memory accesses inevitably increase lookup runtime when the index outsiz ...

VLDB Endowment Inc.2017

A Scala Library for Testing Student Assignments on Concurrent Programming

Mikaël Mayer, Ravichandhran Kandhadai Madhavan

We present a lightweight library for testing concurrent Scala programs by systematically exploring multiple interleavings between user-specified operations on shared objects. Our library is targeted at beginners of concurrent programming in Scala, runs on ...

Assoc Computing Machinery2016

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Green thread

Thread-Placement Learning

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Biomolecular Simulation: a Perspective from High Performance Computing

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Interleaving with Coroutines: A Practical Approach for Robust Index Joins

A Scala Library for Testing Student Assignments on Concurrent Programming

Graph Chatbot

Chattez avec Graph Search

Interleaving with Coroutines: A Practical Approach for Robust Index Joins

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

A Scala Library for Testing Student Assignments on Concurrent Programming

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Biomolecular Simulation: a Perspective from High Performance Computing

Thread-Placement Learning

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores