Publications associées à Celeron

A Visionary Look at the Security of Reconfigurable Cloud Computing

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Paolo Ienne, Mikhail Asiatici

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Cunxi Yu, Maciej Jerzy Ciesielski

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic with ...

IEEE2018

A portable platform for accelerated PIC codes and its application to GPUs using OpenACC

Laurent Villard, Stephan Brunner, Emmanuel Lanti, Trach-Minh Tran, Claudio Gheller

We present a portable platform, called PIC_ENGINE, for accelerating Particle-In-Cell (PIC) codes on heterogeneous many-core architectures such as Graphic Processing Units (GPUs). The aim of this development is efficient simulations on future exascale syste ...

Elsevier Science Bv2016

Caching Gaussians: Minimizing Total Correlation on the Gray–Wyner Network

Michael Christoph Gastpar, Guillaume Jean Op 't Veld

We study a caching problem that resembles a lossy Gray–Wyner network: A source produces vector samples from a Gaussian distribution, but the user is interested in the samples of only one component. The encoder first sends a cache message without any knowle ...

Ieee2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

High Frequency Instrument data processing

Xin Chen, Julien Lesgourgues, Fabio Finelli

We describe the processing of the 531 billion raw data samples from the High Frequency Instrument (HFI), which we performed to produce six temperature maps from the first 473 days of Planck-HFI survey data. These maps provide an accurate rendition of the s ...

Edp Sciences S A2014

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Celeron

A Visionary Look at the Security of Reconfigurable Cloud Computing

Nonlinear Inverse Problems in Quantitative Phase Imaging

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

End-to-End Industrial Study of Retiming

A portable platform for accelerated PIC codes and its application to GPUs using OpenACC

Caching Gaussians: Minimizing Total Correlation on the Gray–Wyner Network

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

High Frequency Instrument data processing

Graph Chatbot

Chattez avec Graph Search

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Caching Gaussians: Minimizing Total Correlation on the Gray–Wyner Network

High Frequency Instrument data processing

A Visionary Look at the Security of Reconfigurable Cloud Computing

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

A portable platform for accelerated PIC codes and its application to GPUs using OpenACC

End-to-End Industrial Study of Retiming

Nonlinear Inverse Problems in Quantitative Phase Imaging

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS