Publications associées à AMD K5

Decoding of error-related potentials in continuous feedback protocols for personalized human computer interaction

The ability to notice erroneous behavior is crucial for effective training. Within the framework of neuroprosthetics, numerous studies in electroencephalography (EEG) confirm the existence of neural correlates when humans perceive the erroneous actions of ...

EPFL2021

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

An Analysis of Database System Performance on Chip Multiprocessors

Anastasia Ailamaki, Babak Falsafi, Frederick Ryan Johnson, Ippokratis Pandis

Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of integration have enabled the advent of chip multiprocessors and ...

2007

Database Servers on Chip Multiprocessors: Limitations and Opportunities

Anastasia Ailamaki, Babak Falsafi, Frederick Ryan Johnson, Ippokratis Pandis

Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of integration have enabled the advent of chip multiprocessors and ...

2007