Performances (informatique)

Résumé

In computing, computer performance is the amount of useful work accomplished by a computer system. Outside of specific contexts, computer performance is estimated in terms of accuracy, efficiency and speed of executing computer program instructions. When it comes to high computer performance, one or more of the following factors might be involved: Short response time for a given piece of work. High throughput (rate of processing work). Low utilization of computing resource(s). Fast (or highly compact) data compression and decompression. High availability of the computing system or application. High bandwidth. Short data transmission time. The performance of any computer system can be evaluated in measurable, technical terms, using one or more of the metrics listed above. This way the performance can be Compared relative to other systems or the same system before/after changes In absolute terms, e.g. for fulfilling a contractual obligation Whilst the above definition relates to a scientific, technical approach, the following definition given by Arnold Allen would be useful for a non-technical audience: The word performance in computer performance means the same thing that performance means in other contexts, that is, it means "How well is the computer doing the work it is supposed to do?" Computer software performance, particularly software application response time, is an aspect of software quality that is important in human–computer interactions. Performance engineering within systems engineering encompasses the set of roles, skills, activities, practices, tools, and deliverables applied at every phase of the systems development life cycle which ensures that a solution will be designed, implemented, and operationally supported to meet the performance requirements defined for the solution. Performance engineering continuously deals with trade-offs between types of performance. Occasionally a CPU designer can find a way to make a CPU with better overall performance by improving one of the aspects of performance, presented below, without sacrificing the CPU's performance in other areas.

Source officielle

https://fr.wikipedia.org/wiki/Performances_(informatique)

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Publications associées (11)

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Charly Nicolas Lucien Castes

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with advanced runtime systems allow the programmer to write a sequential algorithm independently of the hardware architecture in a productive and portable manner, and let a third party software layer -the runtime system- deal with the burden of scheduling a correct, parallel execution of that algorithm to ensure performance. Many HPC algorithms have successfully been implemented following this paradigm, as a testimony of its effectiveness. Developing algorithms that specifically require fine-grained tasks along this model is still considered prohibitive, however, due to per-task management overhead [1], forcing the programmer to resort to a less abstract, and hence more complex "task+X" model. We thus investigate the possibility to offer a tailored execution model, trading dynamic mapping for efficiency by using a decentralized, conservative in-order execution of the task flow, while preserving the benefits of relying on the sequential taskbased programming model. We propose a formal specification of the execution model as well as a prototype implementation, which we assess on a shared-memory multicore architecture with several synthetic workloads. The results show that under the condition of a proper task mapping supplied by the programmer, the pressure on the runtime system is significantly reduced and the execution of fine-grained task flows is much more efficient.

IEEE COMPUTER SOC2022

Starting with Upgrade 1 in 2021, LHCb will move to a purely software-based trigger system. Therefore, the new trigger strategy is to process events at the full rate of 30MHz. Given that the increase of CPU performance has slowed down in recent years, the predicted performance of the software trigger currently falls short of the necessary 30MHz throughput. To cope with this shortfall, the Upgrade High Level Trigger currently uses impact parameter cuts on VELO tracks to reduce the amount of tracks which require further processing. The presented work introduces an alternative approach to determine the impact parameter while achieving a more reliable uncertainty prediction than the current method, which could potentially improve the physics quality of these cuts at a later time.

E D P SCIENCES2019

With more devices becoming mobile, power consumption of communication becomes crucial. Wake-up receivers present an energy-ecient way of detecting incoming transmissions while at the same time the main radio can be fully powered down. After detection the rest of the circuit is activated in order to receive the transmission. Since the digital correlator is the main power consumer of a wake-up receiver, this work compares dierent correlator architectures in terms of their power performance. The correlator architectures are implemented in MATLAB for an analysis of their detection performance and later on in VHDL. A full front and back end implementation is made in order to extract the power performance of the architectures. Large parts of the work ow are automated, allowing to see immediately the impact of multiple parameters such as the sample resolution. Using an equation-based approach, the obtained power estimation is scaled into a sub-threshold region allowing to compare the power performance at very low voltage. The result of our architecture analysis shows that the positioning of the ip- ops is crucial to the power performance: combinational paths should be kept short, in contrast adding additional register to increase speed is benecial. Using large and complex logic decreases the power performance. For the analyzed correlator designs, the inversed structure splitting up the adder chain, which sums the correlation results, performed best. If noise is no issue, using a sample resolution of 1 bit leads to further improvement. Comparing the architectures in the sub-threshold region, fast architectures are less power benecial. A pipelined structure seems to oer a good trade-o between combinational circuit and amount of registers used and has therefore the lowest power consumption.

2014

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Personnes associées (10)

Seyed Armin Tajalli, David Atienza Alonso, Babak Falsafi, Anastasia Ailamaki, Nicola Marzari, Alcherio Martinoli, Christian Enz, James Richard Larus, Marina Zapater Sancho, Yusuf Leblebici

Unités associées (5)

Laboratoire des systèmes embarqués

Laboratoire de systèmes et algorithmes intelligents distribués

Laboratoire des systèmes intégrés (STI/IC)

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Concepts associés (46)

Cycles per instruction

In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is one aspect of a processor's performance: the average number of clock cycles per instruction for a program or program fragment. It is the multiplicative inverse of instructions per cycle. The average of Cycles Per Instruction in a given process (CPI) is defined by the following weighted average: Where is the number of instructions for a given instruction type , is the clock-cycles for that instruction type and is the total instruction count.

Performances (informatique)

En informatique, les performances énoncent les indications chiffrées mesurant les possibilités maximales ou optimales d'un matériel, d'un logiciel, d'un système ou d'un procédé technique pour exécuter une tâche donnée. Selon le contexte, les performances incluent les mesures suivantes : Un faible temps de réponse pour effectuer une tâche donnée Un débit élevé (vitesse d'exécution d'une tâche) L'efficience : faible utilisation des ressources informatiques : processeur, mémoire, stockage, réseau, consommation électrique, etc.

Performance engineering

Performance engineering encompasses the techniques applied during a systems development life cycle to ensure the non-functional requirements for performance (such as throughput, latency, or memory usage) will be met. It may be alternatively referred to as systems performance engineering within systems engineering, and software performance engineering or application performance engineering within software engineering.

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Cours associés (29)

Séances de cours associées (171)

MOOCs associés (4)