Publications de Yusuf Leblebici

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Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Seyed Armin Tajalli, Yusuf Leblebici

A sixth-order low-pass

g_m

-C filter with a very wide tuning range (

f_c

= 100 Hz to 10 MHz) is presented. The wide tuning range has been achieved without using switchable components or programmable building blocks. A single stage folded-cascode transcon ...

Institute of Electrical and Electronics Engineers2011

Yusuf Leblebici

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Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

VHDL-AMS Model of an Electrochemical Cell to Design VLSI Bio-Chips

Design Methods and Tools for 3D Integration

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

3D Integration Technology for Lab-on-a-Chip Applications

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling

Die-Level TSV Fabrication Platform for CMOS-MEMS Integration

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

3D Integration Technology for Lab-on-a-Chip Applications

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Die-Level TSV Fabrication Platform for CMOS-MEMS Integration

Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling

VHDL-AMS Model of an Electrochemical Cell to Design VLSI Bio-Chips

Design Methods and Tools for 3D Integration