Ajay Kumar Verma

Cette personne n’est plus à l’EPFL

Publications associées (15)

À propos
Confidentialité
Mentions légales

Graph Chatbot

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Alessandro Cevrero, Panagiotis Athanasopoulos, Ajay Kumar Verma, Hadi Parandeh Afshar

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008

Fast, quasi-optimal, and pipelined instruction-set extensions

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, the AFUs must satisfy certain constraints in terms of read and write ports betw ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Progressive decomposition: A heuristic to structure arithmetic circuits

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

2007

Design of Low-Power DPA-Resistant Cryptographic Functional Units

Paolo Ienne, Yusuf Leblebici, Ajay Kumar Verma, Zeynep Toprak Deniz

2005

Page 2 sur 2

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Alessandro Cevrero, Panagiotis Athanasopoulos, Ajay Kumar Verma, Hadi Parandeh Afshar

ACM2008