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Ilhan Hatirnaz

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Publications associées (7)

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Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Giovanni De Micheli, David Atienza Alonso, Yusuf Leblebici, Srinivasan Murali, Stéphane Badel, Ilhan Hatirnaz

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for u ...

ACM Press New York, NY, US2007

One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the ...

EPFL2006

Via-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Part I - Circuit Design

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers high speed operation, very high noise immunity, as w ...

2006

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers very high noise immunity due to the differential ope ...

2006

Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiali ...

2005

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This paper describes the design and semi-automated generation of a MOS current-mode logic standard cell library. A set of generic components implementing a wide range of combinational and sequential functions is proposed. The layout of the generic componen ...

2005

We present a new scalable architecture for the realization of fully programmable rank order filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in th ...

2000