Seyed Armin Tajalli

Publications associées (48)

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Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

Seyed Armin Tajalli, Yusuf Leblebici

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS cir ...

2009

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

Seyed Armin Tajalli, Yusuf Leblebici, Zeynep Toprak Deniz, Omer Can Akgun, Thomas Liechti

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...

IEEE2008

Pico-Watt Source-Coupled Logic Circuits

Seyed Armin Tajalli, Yusuf Leblebici

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on d ...

2008

Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications

Seyed Armin Tajalli, Eric Vittoz, Yusuf Leblebici

This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...

2008

Implementing Ultra-high-Value Floating Tunable CMOS Resistors

Seyed Armin Tajalli, Yusuf Leblebici

A compact high-value ﬂoating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 um CMOS technology to verify the proposed concept. This technique has been applied to design a reconﬁgurable sixt ...

2008

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

Seyed Armin Tajalli, Yusuf Leblebici, Mohammad Beikahmadi

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data co ...

NORCHIP2008

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

Seyed Armin Tajalli, Yusuf Leblebici

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach ha ...

IEEE2008

Wide tuning range linearity improved biquadratic transconductor-C filter

Seyed Armin Tajalli, Yusuf Leblebici

This article presents a new technique for improving the linearity performance in biquadratic transconductor-C filters. This improvement has been achieved by applying some modifications to the filter topology which considerably relaxes the linearity require ...

2007

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Seyed Armin Tajalli, Paul Victor Georges Muller, Yusuf Leblebici

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

Seyed Armin Tajalli, Eric Vittoz, Yusuf Leblebici

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold ...

2007

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A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Seyed Armin Tajalli, Paul Victor Georges Muller, Yusuf Leblebici

2007

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

Seyed Armin Tajalli, Eric Vittoz, Yusuf Leblebici

2007